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Currently for samd21 some features are disable because of limited memory.
With the ability to trade firmware and filesystem space, a user may wish to
selectively enable some of these features.  This change allows them to be
enabled in board `mpconfigboard.h` or on the build command line for
example.  The selectively enable functions are: MICROPY_PY_FRAMEBUF,
MICROPY_PY_SELECT, MICROPY_PY_ONEWIRE and MICROPY_PY_ASYNCIO.
Signed-off-by: Rick Sorensen <rick.sorensen@gmail.com>

When MicroPython is used as a submodule and built from the containing
project, e.g. for the embed port, `make submodules` fails because it goes
looking for the sub-sub-module paths in the outer repository instead of in
the micropython repository. Fix this by invoking git inside the micropython
submodule.
Signed-off-by: Christian Walther <cwalther@gmx.ch>

The original OSPIFLASH settings in the `mpconfigboard.h` contained some
mistakes that prevented the firmware from compiling.  These are now
corrected and the firmware can be built with support for OSPI flash.

Note: external storage in OSPI flash is not yet configured on this board.
Signed-off-by: nspsck <teng.jiang94@gmail.com>

Added a #if-block to `system_stm32.c` to check whether
`MICROPY_HW_RCC_OSPI_CLKSOURCE` is defined.  If that is the case, the
clock source for the OSPI will be changed to the specified source.
Signed-off-by: nspsck <teng.jiang94@gmail.com>

Added a if-statement to `octospi.c` to detect if the targeted MCU is one of
the STM32H7 series.  If that is the case, another set of variables are used
for the `mp_hal_pin_config_alt_static_speed()` function, as well as for
register `OCTOSPI1->CR`.  This allows the STM32H723 and STM32H7B3 series
MCU to use octo-spi flash like the STM32H573 series MCU.
Signed-off-by: nspsck <teng.jiang94@gmail.com>

Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>

There is a gap in support for the PVD interrupt on STM32WBxx and STM32WLxx.
This has been tested on NUCLEO_WB55 with the example code:

    from pyb import Pin, ExtInt

    def callback(line):
        print(line)

    PVD = 16
    exti = ExtInt(PVD, ExtInt.IRQ_RISING_FALLING, Pin.PULL_DOWN, callback)

    exti.swint()

Before this commit the CPU locks up as soon as the final line is run.
After this commit it prints "16".

Fixes issue #15548.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>

There are some missing images at MicroPython Downloads.  This commit
attempts to resolve all the current issues, and add product URLs where
missing.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com>

IDF 3 builds are very old now (it seems like the last successful builds are
from 2021), and the current IDF 5 is stable.  So remove IDF 3 variants.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com>

There is no such variant.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com>

By default, the peripheral clock for UART and SPI is set to 48 MHz and will
not be affected by the MCU clock change.  This can be changed by a second
argument to `machine.freq(freq, peripheral_freq)`.  The second argument
must be either 48 MHz or identical with the first argument.

Note that UART and SPI baud rates may have to be re-configured after
changing the MCU clock.
Signed-off-by: robert-hh <robert@hammelrath.com>

As a side effect, the peripheral clock will be set to 48Mhz and both UART
and I2C will not be affected by CPu speed changed using `machine.freq()`.

With the change the UART baud rate range is 50 to 3_000_000.
Signed-off-by: robert-hh <robert@hammelrath.com>

If `MICROPY_PY_THREAD` is set to 0 (ie: a user C module wishes to use core1
exclusively) then the test of `core1_entry` would fail to compile with an
"undeclared identifier" error.  Fix it by wrapping in `MICROPY_PY_THREAD`.
Signed-off-by: Phil Howard <phil@gadgetoid.com>

Telling that subseconds is not supported and returns always 0.  This was
changed in 913f9ad5.
Signed-off-by: robert-hh <robert@hammelrath.com>

Preventing already pending IRQs to fire when not expected.
Signed-off-by: robert-hh <robert@hammelrath.com>

Signed-off-by: robert-hh <robert@hammelrath.com>

The RV32 emitter used an additional temporary register, as certain code
sequences required extra storage.  This commit removes its usage in all
but one case, using REG_TEMP2 instead.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

The RV32 emitter sometimes generated short load opcodes even when it
was not supposed to.  This commit fixes an off-by-one error in its
offset eligibility range calculation and corrects one case of offset
calculation, operating on the raw label index number rather than its
effective offset in the stack (C.LW assumes all loads are
word-aligned).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

The RV32 emitter always scheduled short jumps even outside the emit
compiler pass.  Running the full test suite through the native emitter
instead of just the tests that depend on the emitter at runtime (as in,
`micropython/native_*` and `micropython/viper_* tests`) uncovered more
places where the invalid behaviour was still present.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

Skip whitespace characters between pairs of hex numbers.
This makes `bytes.fromhex()` compatible with cpython.

Includes simple test in `tests/basic/builtin_str_hex.py`.
Signed-off-by: Glenn Moloney <glenn.moloney@gmail.com>

Signed-off-by: Elvis Pfützenreuter <epxx@epxx.co>

Signed-off-by: Matt Trentini <matt.trentini@gmail.com>

The extra limit for C3 dates from 68235148 which added C3 support.
Measuring the minimum stack margins that can pass the stress tests I
measured 768 bytes for ESP32-S3 and 512 bytes for ESP32-C3 on ESP-IDF
V5.2.2 and similar on V5.0.4. i.e. The ESP32-C3 actually needs less stack
margin not more!

I think the extra margin for ESP32-C3 probably arose from:

1. Some toolchain inefficiency in the IDF V4.x RISC-V compiler codegen,
that has since been improved.

OR

2. The race condition that was fixed in e3955f42 where sometimes the limit
wasn't set correctly at all. This seems to trigger more on C3, presumably
some timing artifact, and I'd believe that some binaries might be more
susceptible than others due to random factors.

OR

3. Commit 6007f3e2 which enabled custom
NLR handling for ESP32-C3.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

This value should have been adjusted when the new cstack API was adopted in
e3955f42, as otherwise the stack limit is too small especially on
ESP32-C3 where the stack limit was 6144 - 2048 - 2048.

Some extra margin is needed for bluetooth irq because invoke_irq_handler()
isn't a top-level task function, NimBLE calls through multiple layers
first. Measuring this overhead on IDF V5.2.2 (by putting an abort() in
invoke_irq_handler() and then measuring the stack size) yielded 672 bytes
on ESP32-S3 and 612 bytes on ESP32-C3, similar to the size reported in
cd66aa05.

Sticking with 1024 bytes for added safety margin. This means on Xtensa the
total margin for the BLE task stays the same (2048 bytes) as before
switching to cstack.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

If verbose debugging is enabled there is some stdout output happening
before the GIL is ready (for example, GC initialisation), and the code
assumed that no string printing occurred before the interpreter was fully
initialised.  Printing long strings would operate without holding the GIL,
which would crash if string output would happen too early in the startup
process.

This commit addresses that issue, making sure verbose debugging output will
work even before the interpreter is fully initialised (as if it is not yet
ready there's no GIL to take care of).

Also, the threshold that would indicate whether a string is "long" (and
thus requiring a GIL release/lock operation) or not was hardcoded to 20
bytes.  This commit makes that configurable, maintaining 20 bytes as a
default.

Fixes issue #15408.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

Fixes issue #15618.
Signed-off-by: Matt Trentini <matt.trentini@gmail.com>

Commit a66bd7a4 added the
ESP32_GENERIC_C3_USB board (now merged with ESP32_GENERIC_C3) and changed
the brownout detector from the default level 7 (~2.51V) to level 4
(~2.92V).

Raising the level again seems to fix random BOD resets on some of the
cheaper ESP32-C3 dev boards (that likely skimp on power supply
capacitance).

Specifically, this change prevents random resets running multi_bluetooth
tests on ESP32-C3 "SuperMini" board.

Also removed from the LOLIN_C3_MINI board as it seems this config is a copy
of the generic one.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

The ESP-IDF default on C3 is primary UART0, secondary USB serial/jtag.
Previously MicroPython configured the primary as USB Serial/JTAG and
manually worked with the UART0 console. However UART0 console stopped
working this way in v5.2.2.

The big change is that CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG is no longer set,
as primary console is UART0. However
CONFIG_ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG is set and IDF provides a
macro CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED which is set if either
primary or secondary esp_console is USB serial/jtag. So need to use that
macro instead.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Keeping older versions, however if the update goes well then these may be
dropped in the future.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Signed-off-by: Angus Gratton <angus@redyak.com.au>

Saves code size, MicroPython doesn't appear to rely on any of the missing
formatters (64-bit integers, c99-style named arguments).
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Replaces the deprecated ESP32 calibration API with the "line" method
instead.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Disable unnecessary IRAM ISR functionality.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

This new calibration routine exists for S3 in v5.1.1.  It works for all
platforms in 5.2.1.
Signed-off-by: Andrew Leech <andrew@alelec.net>

Update to the test added in 1e98c4cb,
changes the SPI pins for ESP32-C3 (IO 18 and 19 are the native USB pins).
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Necessary to pass CI when testing the V2 preview APIs.

Also adds an extra coverage test for the legacy stackctrl API, to maintain
coverage and check for any regression.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Now passing on ESP32-S3 and ESP32-C3.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

This change moves that complexity out into the stack checker and fixes the
bug where stack margin wasn't set correctly by ESP32-C3 threads.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

Currently the stack limit margin is hard-coded in each port's call to
`mp_stack_set_limit()`, but on threaded ports it's fiddlier and can lead to
bugs (such as incorrect thread stack margin on esp32).

This commit provides a new API to initialise the C Stack in one function
call, with a config macro to set the margin.  Where possible the new call
is inlined to reduce code size in thread-free ports.

Intended replacement for `MP_TASK_STACK_LIMIT_MARGIN` on esp32.

The previous `stackctrl.h` API is still present and unmodified apart from a
deprecation comment.  However it's not available when the
`MICROPY_PREVIEW_VERSION_2` macro is set.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>