esp32: Remove the increased stack limit margin for ESP32-C3.

The extra limit for C3 dates from 68235148 which added C3 support.
Measuring the minimum stack margins that can pass the stress tests I
measured 768 bytes for ESP32-S3 and 512 bytes for ESP32-C3 on ESP-IDF
V5.2.2 and similar on V5.0.4. i.e. The ESP32-C3 actually needs less stack
margin not more!

I think the extra margin for ESP32-C3 probably arose from:

1. Some toolchain inefficiency in the IDF V4.x RISC-V compiler codegen,
that has since been improved.

OR

2. The race condition that was fixed in e3955f42 where sometimes the limit
wasn't set correctly at all. This seems to trigger more on C3, presumably
some timing artifact, and I'd believe that some binaries might be more
susceptible than others due to random factors.

OR

3. Commit 6007f3e2 which enabled custom
NLR handling for ESP32-C3.

This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>

ports/esp32/mpconfigport.h

@@ -62,11 +62,7 @@
 // Python internal features
 #define MICROPY_READER_VFS                  (1)
 #define MICROPY_ENABLE_GC                   (1)
-#if CONFIG_IDF_TARGET_ARCH_RISCV                   // RISC-V SoCs use more stack than Xtensa
-#define MICROPY_STACK_CHECK_MARGIN          (2048) // This may be unnecessarily conservative
-#else
 #define MICROPY_STACK_CHECK_MARGIN          (1024)
-#endif
 #define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1)
 #define MICROPY_LONGINT_IMPL                (MICROPY_LONGINT_IMPL_MPZ)
 #define MICROPY_ERROR_REPORTING             (MICROPY_ERROR_REPORTING_NORMAL)