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arduino-nRF5
Commit a55d33dd authored by Sandeep Mistry's avatar Sandeep Mistry
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Update to Nordic SDK 11

parent 5a400abf
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cores/nRF52/binary.h
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/device/compiler_abstraction.h
View file @ a55d33dd
......@@ -33,92 +33,92 @@
/*lint ++flb "Enter library region" */
#if defined ( __CC_ARM )
#ifndef __ASM
#define __ASM __asm
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#define __INLINE __inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#define __WEAK __weak
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#define __ALIGN(n) __align(n)
#endif
#define GET_SP() __current_sp()
#define GET_SP() __current_sp()
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __weak
#define __WEAK __weak
#endif
/* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */
#ifndef __ALIGN
#define __ALIGN(n)
#define __ALIGN(n)
#endif
#define GET_SP() __get_SP()
#define GET_SP() __get_SP()
#elif defined ( __GNUC__ )
#ifndef __ASM
#define __ASM __asm
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __attribute__((aligned(n)))
#define __ALIGN(n) __attribute__((aligned(n)))
#endif
#define GET_SP() gcc_current_sp()
#define GET_SP() gcc_current_sp()
static inline unsigned int gcc_current_sp(void)
{
register unsigned sp __ASM("sp");
return sp;
}
#elif defined ( __TASKING__ )
#ifndef __ASM
#define __ASM __asm
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#define __INLINE inline
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#define __WEAK __attribute__((weak))
#endif
#ifndef __ALIGN
#define __ALIGN(n) __align(n)
#define __ALIGN(n) __align(n)
#endif
#define GET_SP() __get_MSP()
#define GET_SP() __get_MSP()
#endif
/*lint --flb "Leave library region" */
......
cores/nRF52/nRF52_SDK_0/components/device/nrf.h
View file @ a55d33dd
......@@ -31,11 +31,16 @@
#ifndef NRF_H
#define NRF_H
#if defined(_WIN32)
/* MDK version */
#define MDK_MAJOR_VERSION 8
#define MDK_MINOR_VERSION 5
#define MDK_MICRO_VERSION 0
#if defined(_WIN32)
/* Do not include nrf51 specific files when building for PC host */
#elif defined(__unix)
#elif defined(__unix)
/* Do not include nrf51 specific files when building for PC host */
#elif defined(__APPLE__)
#elif defined(__APPLE__)
/* Do not include nrf51 specific files when building for PC host */
#else
......@@ -48,6 +53,7 @@
#include "nrf52.h"
#include "nrf52_bitfields.h"
#include "nrf51_to_nrf52.h"
#include "nrf52_name_change.h"
#else
#error "Device family must be defined. See nrf.h."
#endif /* NRF51, NRF52 */
......
cores/nRF52/nRF52_SDK_0/components/device/nrf51.h
View file @ a55d33dd
......@@ -6,10 +6,10 @@
* nrf51 from Nordic Semiconductor.
*
* @version V522
* @date 15. June 2015
* @date 23. February 2016
*
* @note Generated with SVDConv V2.81d
* from CMSIS SVD File 'nrf51.xml' Version 522,
* from CMSIS SVD File 'nrf51.svd' Version 522,
*
* @par Copyright (c) 2013, Nordic Semiconductor ASA
* All rights reserved.
......@@ -542,39 +542,41 @@ typedef struct { /*!< SPIS Structure
__O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
__I uint32_t RESERVED1[54];
__IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
__I uint32_t RESERVED2[8];
__I uint32_t RESERVED2[2];
__IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
__I uint32_t RESERVED3[5];
__IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
__I uint32_t RESERVED3[53];
__I uint32_t RESERVED4[53];
__IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
__I uint32_t RESERVED4[64];
__I uint32_t RESERVED5[64];
__IO uint32_t INTENSET; /*!< Interrupt enable set register. */
__IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
__I uint32_t RESERVED5[61];
__I uint32_t RESERVED6[61];
__I uint32_t SEMSTAT; /*!< Semaphore status. */
__I uint32_t RESERVED6[15];
__I uint32_t RESERVED7[15];
__IO uint32_t STATUS; /*!< Status from last transaction. */
__I uint32_t RESERVED7[47];
__I uint32_t RESERVED8[47];
__IO uint32_t ENABLE; /*!< Enable SPIS. */
__I uint32_t RESERVED8;
__I uint32_t RESERVED9;
__IO uint32_t PSELSCK; /*!< Pin select for SCK. */
__IO uint32_t PSELMISO; /*!< Pin select for MISO. */
__IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
__IO uint32_t PSELCSN; /*!< Pin select for CSN. */
__I uint32_t RESERVED9[7];
__I uint32_t RESERVED10[7];
__IO uint32_t RXDPTR; /*!< RX data pointer. */
__IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
__I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
__I uint32_t RESERVED10;
__I uint32_t RESERVED11;
__IO uint32_t TXDPTR; /*!< TX data pointer. */
__IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
__I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
__I uint32_t RESERVED11;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED12;
__IO uint32_t CONFIG; /*!< Configuration register. */
__I uint32_t RESERVED13;
__IO uint32_t DEF; /*!< Default character. */
__I uint32_t RESERVED13[24];
__I uint32_t RESERVED14[24];
__IO uint32_t ORC; /*!< Over-read character. */
__I uint32_t RESERVED14[654];
__I uint32_t RESERVED15[654];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_SPIS_Type;
......@@ -863,8 +865,8 @@ typedef struct { /*!< AAR Structure
__IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
__I uint32_t RESERVED5;
__IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
during resolution. A minimum of 3 bytes must be reserved. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
resolution. A minimum of 3 bytes must be reserved. */
__I uint32_t RESERVED6[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_AAR_Type;
......@@ -902,8 +904,8 @@ typedef struct { /*!< CCM Structure
__IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
__IO uint32_t INPTR; /*!< Pointer to the input packet. */
__IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
during resolution. A minimum of 43 bytes must be reserved. */
__IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
resolution. A minimum of 43 bytes must be reserved. */
__I uint32_t RESERVED5[697];
__IO uint32_t POWER; /*!< Peripheral power control. */
} NRF_CCM_Type;
......
cores/nRF52/nRF52_SDK_0/components/device/nrf51_bitfields.h
View file @ a55d33dd
......@@ -5960,6 +5960,13 @@
#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 4 : enable interrupt on ENDRX event. */
#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
/* Bit 1 : Enable interrupt on END event. */
#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
......@@ -5977,6 +5984,13 @@
#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 4 : Disable interrupt on ENDRX event. */
#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
/* Bit 1 : Disable interrupt on END event. */
#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
......
cores/nRF52/nRF52_SDK_0/components/device/nrf52_name_change.h 0 → 100755
View file @ a55d33dd
/* Copyright (c) 2015, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* * Neither the name of Nordic Semiconductor ASA nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef NRF52_NAME_CHANGE_H
#define NRF52_NAME_CHANGE_H
/*lint ++flb "Enter library region */
/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and
* nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
* macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
*/
/* I2S */
/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
#define I2S_ENABLE_ENABLE_DISABLE I2S_ENABLE_ENABLE_Disabled
#define I2S_ENABLE_ENABLE_ENABLE I2S_ENABLE_ENABLE_Enabled
#define I2S_CONFIG_MODE_MODE_MASTER I2S_CONFIG_MODE_MODE_Master
#define I2S_CONFIG_MODE_MODE_SLAVE I2S_CONFIG_MODE_MODE_Slave
#define I2S_CONFIG_RXEN_RXEN_DISABLE I2S_CONFIG_RXEN_RXEN_Disabled
#define I2S_CONFIG_RXEN_RXEN_ENABLE I2S_CONFIG_RXEN_RXEN_Enabled
#define I2S_CONFIG_TXEN_TXEN_DISABLE I2S_CONFIG_TXEN_TXEN_Disabled
#define I2S_CONFIG_TXEN_TXEN_ENABLE I2S_CONFIG_TXEN_TXEN_Enabled
#define I2S_CONFIG_MCKEN_MCKEN_DISABLE I2S_CONFIG_MCKEN_MCKEN_Disabled
#define I2S_CONFIG_MCKEN_MCKEN_ENABLE I2S_CONFIG_MCKEN_MCKEN_Enabled
#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT I2S_CONFIG_SWIDTH_SWIDTH_8Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT I2S_CONFIG_SWIDTH_SWIDTH_16Bit
#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT I2S_CONFIG_SWIDTH_SWIDTH_24Bit
#define I2S_CONFIG_ALIGN_ALIGN_LEFT I2S_CONFIG_ALIGN_ALIGN_Left
#define I2S_CONFIG_ALIGN_ALIGN_RIGHT I2S_CONFIG_ALIGN_ALIGN_Right
#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED I2S_CONFIG_FORMAT_FORMAT_Aligned
#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT I2S_CONFIG_CHANNELS_CHANNELS_Left
#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT I2S_CONFIG_CHANNELS_CHANNELS_Right
/*lint --flb "Leave library region" */
#endif /* NRF52_NAME_CHANGE_H */
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_adc.c
View file @ a55d33dd
......@@ -22,10 +22,10 @@
/**
* @brief Function for configuring ADC.
*
* This function power on ADC and configure it. ADC is in DISABLE state after configuration,
* This function powers on ADC and configures it. ADC is in DISABLE state after configuration,
* so it should be enabled before using it.
*
* @param[in] config is requested configuration
* @param[in] config Requested configuration.
*/
void nrf_adc_configure(nrf_adc_config_t * config)
{
......@@ -51,14 +51,14 @@ void nrf_adc_configure(nrf_adc_config_t * config)
/**
* @brief Blocking function for executing single ADC conversion.
*
* This function selects desired input, starts single conversion,
* waits for its finish and returns result.
* ADC is left in STOP state, given input is selected.
* This function selects the desired input, starts a single conversion,
* waits for it to finish, and returns the result.
* ADC is left in STOP state, the given input is selected.
* This function does not check if ADC is initialized and powered.
*
* @param[in] input is requested input to be selected
* @param[in] input Requested input to be selected.
*
* @return conversion result
* @return Conversion result
*/
int32_t nrf_adc_convert_single(nrf_adc_config_input_t input)
{
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_adc.h
View file @ a55d33dd
......@@ -10,19 +10,14 @@
*
*/
/**
* @file
* @brief ADC HAL API.
*/
#ifndef NRF_ADC_H_
#define NRF_ADC_H_
/**
* @defgroup nrf_adc ADC HAL
* @defgroup nrf_adc_hal ADC HAL
* @{
* @ingroup nrf_drivers
* @brief Hardware abstraction layer for managing the analog-to-digital converter.
* @ingroup nrf_adc
* @brief @tagAPI51 Hardware access layer for managing the analog-to-digital converter (ADC).
*/
#include <stdbool.h>
......@@ -30,11 +25,20 @@
#include "nrf.h"
#ifndef NRF52
/**
* @enum nrf_adc_config_resolution_t
* @enum nrf_adc_config_resolution_t
* @brief Resolution of the analog-to-digital converter.
*/
#ifndef NRF52
/**
* @brief ADC interrupts.
*/
typedef enum
{
NRF_ADC_INT_END_MASK = ADC_INTENSET_END_Msk, /**< ADC interrupt on END event. */
} nrf_adc_int_mask_t;
typedef enum
{
NRF_ADC_CONFIG_RES_8BIT = ADC_CONFIG_RES_8bit, /**< 8 bit resolution. */
......@@ -201,35 +205,6 @@ __STATIC_INLINE bool nrf_adc_is_busy(void)
return ( (NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == ADC_BUSY_BUSY_Msk);
}
/**
* @brief Function for enabling interrupts from the ADC.
*
* @param[in] interrupts Mask of interrupts to be enabled.
*
* @sa nrf_adc_int_disable()
* @sa nrf_adc_int_get()
*/
__STATIC_INLINE void nrf_adc_int_enable(uint32_t interrupts)
{
NRF_ADC->INTENSET = interrupts;
}
/**
* @brief Function for disabling interrupts from the ADC.
*
* @param[in] interrupts Mask of interrupts to be disabled.
*
* @sa nrf_adc_int_enable()
* @sa nrf_adc_int_get()
*/
__STATIC_INLINE void nrf_adc_int_disable(uint32_t interrupts)
{
NRF_ADC->INTENCLR = interrupts;
}
/**
* @brief Function for getting the ADC's enabled interrupts.
*
......@@ -284,7 +259,7 @@ __STATIC_INLINE bool nrf_adc_conversion_finished(void)
}
/**
* @brief Function for cleaning conversion end event.
* @brief Function for clearing the conversion END event.
*/
__STATIC_INLINE void nrf_adc_conversion_event_clean(void)
{
......@@ -298,11 +273,7 @@ __STATIC_INLINE void nrf_adc_conversion_event_clean(void)
*
* @return Address of the specified ADC task.
*/
__STATIC_INLINE uint32_t * nrf_adc_task_address_get(nrf_adc_task_t adc_task)
{
return (uint32_t *)((uint8_t *)NRF_ADC + adc_task);
}
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task);
/**
* @brief Function for getting the address of a specific ADC event register.
......@@ -311,11 +282,132 @@ __STATIC_INLINE uint32_t * nrf_adc_task_address_get(nrf_adc_task_t adc_task)
*
* @return Address of the specified ADC event.
*/
__STATIC_INLINE uint32_t * nrf_adc_event_address_get(nrf_adc_event_t adc_event)
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event);
/**
* @brief Function for setting the CONFIG register in ADC.
*
* @param[in] configuration Value to be written to the CONFIG register.
*/
__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration);
/**
* @brief Function for clearing an ADC event.
*
* @param[in] event Event to clear.
*/
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event);
/**
* @brief Function for checking state of an ADC event.
*
* @param[in] event Event to check.
*
* @retval true If the event is set.
* @retval false If the event is not set.
*/
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
/**
* @brief Function for enabling specified interrupts.
*
* @param[in] int_mask Interrupts to enable.
*/
__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask);
/**
* @brief Function for disabling specified interrupts.
*
* @param[in] int_mask Interrupts to disable.
*/
__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask);
/**
* @brief Function for retrieving the state of a given interrupt.
*
* @param[in] int_mask Interrupt to check.
*
* @retval true If the interrupt is enabled.
* @retval false If the interrupt is not enabled.
*/
__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask);
/**
* @brief Function for activating a specific ADC task.
*
* @param[in] task Task to activate.
*/
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
/**
* @brief Function for enabling ADC.
*
*/
__STATIC_INLINE void nrf_adc_enable(void);
/**
* @brief Function for disabling ADC.
*
*/
__STATIC_INLINE void nrf_adc_disable(void);
#ifndef SUPPRESS_INLINE_IMPLEMENTATION
__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task)
{
return (uint32_t)((uint8_t *)NRF_ADC + adc_task);
}
__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event)
{
return (uint32_t *)((uint8_t *)NRF_ADC + adc_event);
return (uint32_t)((uint8_t *)NRF_ADC + adc_event);
}
__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration)
{
NRF_ADC->CONFIG = configuration;
}
__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL;
}
__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event)
{
return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event);
}
__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask)
{
NRF_ADC->INTENSET = int_mask;
}
__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask)
{
NRF_ADC->INTENCLR = int_mask;
}
__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask)
{
return (bool)(NRF_ADC->INTENSET & int_mask);
}
__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task)
{
*((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL;
}
__STATIC_INLINE void nrf_adc_enable(void)
{
NRF_ADC->ENABLE = 1;
}
__STATIC_INLINE void nrf_adc_disable(void)
{
NRF_ADC->ENABLE = 0;
}
#endif
#endif /* NRF52 */
/**
*@}
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_comp.h 0 → 100755
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_egu.h 0 → 100755
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_gpio.h
View file @ a55d33dd
/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
* SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information. NO
* WARRANTY of ANY KIND is provided. This heading must NOT be removed from
* the file.
*
*/
#ifndef NRF_GPIO_H__
#define NRF_GPIO_H__
......@@ -208,7 +219,7 @@ __STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_se
/**
* @brief Function for setting the direction for a GPIO pin.
*
* @param pin_number specifies the pin number [0:31] for which to
* @param pin_number specifies the pin number (0-31) for which to
* set the direction.
*
* @param direction specifies the direction
......@@ -221,40 +232,67 @@ __STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number specifies the pin number [0:31] to
* set.
* @param pin_number Specifies the pin number (0-31) to set.
*/
__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
/**
* @brief Function for setting GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to set.
*/
__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask);
/**
* @brief Function for clearing a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number specifies the pin number [0:31] to
* clear.
* @param pin_number Specifies the pin number (0-31) to clear.
*/
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
/**
* @brief Function for clearing GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to clear.
*/
__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask);
/**
* @brief Function for toggling a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number specifies the pin number [0:31] to
* toggle.
* @param pin_number Specifies the pin number (0-31) to toggle.
*/
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
/**
* @brief Function for toggling GPIO pins.
*
* Note that the pins must be configured as outputs for this
* function to have any effect.
*
* @param pin_mask Specifies the pins to toggle.
*/
__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask);
/**
* @brief Function for writing a value to a GPIO pin.
*
* Note that the pin must be configured as an output for this
* function to have any effect.
*
* @param pin_number specifies the pin number [0:31] to
* @param pin_number specifies the pin number (0-31) to
* write.
*
* @param value specifies the value to be written to the pin.
......@@ -269,7 +307,7 @@ __STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
* Note that the pin must have input connected for the value
* returned from this function to be valid.
*
* @param pin_number specifies the pin number [0:31] to
* @param pin_number specifies the pin number (0-31) to
* read.
*
* @return
......@@ -292,7 +330,7 @@ __STATIC_INLINE uint32_t nrf_gpio_pins_read(void);
/**
* @brief Function for reading the sense configuration of a GPIO pin.
*
* @param pin_number specifies the pin number [0:31] to
* @param pin_number specifies the pin number (0-31) to
* read.
*
* @retval Sense configuration
......@@ -508,26 +546,31 @@ __STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
NRF_GPIO->OUTSET = (1UL << pin_number);
}
__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask)
{
NRF_GPIO->OUTSET = pin_mask;
}
__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
{
NRF_GPIO->OUTCLR = (1UL << pin_number);
}
__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask)
{
NRF_GPIO->OUTCLR = pin_mask;
}
__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
{
const uint32_t pin_bit = 1UL << pin_number;
const uint32_t pin_state = ((NRF_GPIO->OUT >> pin_number) & 1UL);
nrf_gpio_pins_toggle(1UL << pin_number);
}
if (pin_state == 0)
{
// Current state low, set high.
NRF_GPIO->OUTSET = pin_bit;
}
else
{
// Current state high, set low.
NRF_GPIO->OUTCLR = pin_bit;
}
__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask)
{
uint32_t pins_state = NRF_GPIO->OUT;
NRF_GPIO->OUTSET = (~pins_state & pin_mask);
NRF_GPIO->OUTCLR = ( pins_state & pin_mask);
}
__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_gpiote.h
View file @ a55d33dd
......@@ -25,7 +25,7 @@
*/
#ifdef NRF51
#define NUMBER_OF_GPIO_TE 4
#elif defined NRF52
#elif defined(NRF52)
#define NUMBER_OF_GPIO_TE 8
#else
#error "Chip family not specified"
......@@ -62,6 +62,30 @@ typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
NRF_GPIOTE_TASKS_OUT_1 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
NRF_GPIOTE_TASKS_OUT_2 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
NRF_GPIOTE_TASKS_OUT_3 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_TASKS_OUT_4 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
NRF_GPIOTE_TASKS_OUT_5 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
NRF_GPIOTE_TASKS_OUT_6 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
NRF_GPIOTE_TASKS_OUT_7 = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
#endif
#ifdef NRF52
NRF_GPIOTE_TASKS_SET_0 = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
NRF_GPIOTE_TASKS_SET_1 = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
NRF_GPIOTE_TASKS_SET_2 = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
NRF_GPIOTE_TASKS_SET_3 = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
NRF_GPIOTE_TASKS_SET_4 = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
NRF_GPIOTE_TASKS_SET_5 = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
NRF_GPIOTE_TASKS_SET_6 = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
NRF_GPIOTE_TASKS_SET_7 = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
NRF_GPIOTE_TASKS_CLR_0 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
NRF_GPIOTE_TASKS_CLR_1 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
NRF_GPIOTE_TASKS_CLR_2 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
NRF_GPIOTE_TASKS_CLR_3 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
NRF_GPIOTE_TASKS_CLR_4 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
NRF_GPIOTE_TASKS_CLR_5 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
NRF_GPIOTE_TASKS_CLR_6 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
NRF_GPIOTE_TASKS_CLR_7 = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
#endif
/*lint -restore*/
} nrf_gpiote_tasks_t;
......@@ -74,6 +98,12 @@ typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
NRF_GPIOTE_EVENTS_IN_1 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
NRF_GPIOTE_EVENTS_IN_2 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
NRF_GPIOTE_EVENTS_IN_3 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_EVENTS_IN_4 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
NRF_GPIOTE_EVENTS_IN_5 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
NRF_GPIOTE_EVENTS_IN_6 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
NRF_GPIOTE_EVENTS_IN_7 = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
#endif
NRF_GPIOTE_EVENTS_PORT = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**< Port event.*/
/*lint -restore*/
} nrf_gpiote_events_t;
......@@ -88,11 +118,26 @@ typedef enum
NRF_GPIOTE_INT_IN1_MASK = GPIOTE_INTENSET_IN1_Msk, /**< GPIOTE interrupt from IN1. */
NRF_GPIOTE_INT_IN2_MASK = GPIOTE_INTENSET_IN2_Msk, /**< GPIOTE interrupt from IN2. */
NRF_GPIOTE_INT_IN3_MASK = GPIOTE_INTENSET_IN3_Msk, /**< GPIOTE interrupt from IN3. */
#if (NUMBER_OF_GPIO_TE == 8)
NRF_GPIOTE_INT_IN4_MASK = GPIOTE_INTENSET_IN4_Msk, /**< GPIOTE interrupt from IN4. */
NRF_GPIOTE_INT_IN5_MASK = GPIOTE_INTENSET_IN5_Msk, /**< GPIOTE interrupt from IN5. */
NRF_GPIOTE_INT_IN6_MASK = GPIOTE_INTENSET_IN6_Msk, /**< GPIOTE interrupt from IN6. */
NRF_GPIOTE_INT_IN7_MASK = GPIOTE_INTENSET_IN7_Msk, /**< GPIOTE interrupt from IN7. */
#endif
NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
} nrf_gpiote_int_t;
#if (NUMBER_OF_GPIO_TE == 4)
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
#elif (NUMBER_OF_GPIO_TE == 8)
#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
#else
#error "Unexpected number of GPIO Tasks and Events"
#endif
/**
* @brief Function for activating a specific GPIOTE task.
*
......@@ -332,8 +377,8 @@ __STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
{
NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_OUTINIT_Msk;
NRF_GPIOTE->CONFIG[idx] |= (init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk;
NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk)
| ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
}
__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_i2s.h 0 → 100755
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_lpcomp.h
View file @ a55d33dd
......@@ -22,7 +22,7 @@
* @defgroup nrf_lpcomp_hal LPCOMP HAL
* @{
* @ingroup nrf_lpcomp
* @brief Hardware abstraction layer for managing the Low Power Comparator (LPCOMP).
* @brief Hardware access layer for managing the Low Power Comparator (LPCOMP).
*/
#include "nrf.h"
......@@ -259,7 +259,7 @@ __STATIC_INLINE void nrf_lpcomp_int_disable(uint32_t lpcomp_int_mask)
/**
* @brief Function for getting the enabled interrupts of LCOMP.
* @brief Function for getting the enabled interrupts of LPCOMP.
*
* @param[in] lpcomp_int_mask Mask of interrupts to be checked.
*
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_nvmc.c
View file @ a55d33dd
......@@ -16,7 +16,7 @@
*@brief NMVC driver implementation
*/
#include "stdbool.h"
#include <stdbool.h>
#include "nrf.h"
#include "nrf_nvmc.h"
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_pdm.h 0 → 100755
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_ppi.h
View file @ a55d33dd
/* Copyright (c) 2014 Nordic Semiconductor. All Rights Reserved.
/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
*
* The information contained herein is property of Nordic Semiconductor ASA.
* Terms and conditions of usage are described in detail in NORDIC
......@@ -20,7 +20,7 @@
* @defgroup nrf_ppi_hal PPI HAL
* @{
* @ingroup nrf_ppi
* @brief Hardware abstraction layer for setting up Programmable Peripheral Interconnect (PPI) channels.
* @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
*/
#define NRF_PPI_TASK_SET (1UL)
......@@ -47,6 +47,12 @@ typedef enum
NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
#ifdef NRF52
NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
#endif
NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
......@@ -70,7 +76,11 @@ typedef enum
NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
NRF_PPI_CHANNEL_GROUP3 = 3 /**< Channel group 3. */
NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
#ifdef NRF52
NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
NRF_PPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
#endif
} nrf_ppi_channel_group_t;
/**
......@@ -107,7 +117,13 @@ typedef enum
NRF_PPI_TASK_CHG2_EN = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN), /**< Task for enabling channel group 2 */
NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
NRF_PPI_TASK_CHG3_EN = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN), /**< Task for enabling channel group 3 */
NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS) /**< Task for disabling channel group 3 */
NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
#ifdef NRF52
NRF_PPI_TASK_CHG4_EN = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN), /**< Task for enabling channel group 4 */
NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
NRF_PPI_TASK_CHG5_EN = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN), /**< Task for enabling channel group 5 */
NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS) /**< Task for disabling channel group 5 */
#endif
/*lint -restore*/
} nrf_ppi_task_t;
......@@ -170,13 +186,22 @@ __STATIC_INLINE void nrf_ppi_channel_disable_all(void)
NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
}
/**
* @brief Function for disabling multiple PPI channels.
*
* @param[in] mask Channel mask.
*/
__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
{
NRF_PPI->CHENCLR = mask;
}
/**
* @brief Function for setting up event and task endpoints for a given PPI channel.
*
* @param[in] eep Event register address (register value).
* @param[in] eep Event register address.
*
* @param[in] tep Task register address (register value).
* @param[in] tep Task register address.
*
* @param[in] channel Channel to which the given endpoints are assigned.
*/
......@@ -188,6 +213,40 @@ __STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
NRF_PPI->CH[(uint32_t) channel].TEP = tep;
}
#ifdef NRF52
/**
* @brief Function for setting up task endpoint for a given PPI fork.
*
* @param[in] fork_tep Task register address.
*
* @param[in] channel Channel to which the given fork endpoint is assigned.
*/
__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t fork_tep)
{
NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
}
/**
* @brief Function for setting up event and task endpoints for a given PPI channel and fork.
*
* @param[in] eep Event register address.
*
* @param[in] tep Task register address.
*
* @param[in] fork_tep Fork task register address (register value).
*
* @param[in] channel Channel to which the given endpoints are assigned.
*/
__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
uint32_t eep,
uint32_t tep,
uint32_t fork_tep)
{
nrf_ppi_channel_endpoint_setup(channel, eep, tep);
nrf_ppi_fork_endpoint_setup(channel, fork_tep);
}
#endif
/**
* @brief Function for including a PPI channel in a channel group.
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_pwm.h 0 → 100755
View file @ a55d33dd
This diff is collapsed.
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_qdec.h
View file @ a55d33dd
......@@ -12,7 +12,7 @@
#ifndef NRF_QDEC_H__
#define NRF_QDEC_H__
#include "stddef.h"
#include <stddef.h>
#include "nrf_error.h"
#include "nrf.h"
......@@ -22,7 +22,7 @@
* @defgroup nrf_qdec_hal QDEC HAL
* @{
* @ingroup nrf_qdec
* @brief Hardware abstraction layer for accessing the quadrature decoder (QDEC) peripheral.
* @brief Hardware access layer for accessing the quadrature decoder (QDEC) peripheral.
*/
/**
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_rng.h
View file @ a55d33dd
......@@ -21,11 +21,12 @@
* @defgroup nrf_rng_hal RNG HAL
* @{
* @ingroup nrf_rng
* @brief Hardware abstraction layer for managing the random number generator (RNG).
* @brief Hardware access layer for managing the random number generator (RNG).
*/
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
#include "nrf.h"
#define NRF_RNG_TASK_SET (1UL)
......
cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_spis.h 0 → 100755
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cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_twim.h 0 → 100755
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cores/nRF52/nRF52_SDK_0/components/drivers_nrf/hal/nrf_wdt.h
View file @ a55d33dd
......@@ -15,7 +15,7 @@
* @{
* @ingroup nrf_wdt
*
* @brief Hardware abstraction layer for accessing the watchdog timer (WDT) peripheral.
* @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral.
*/
#ifndef NRF_WDT_H__
......
linker_scripts/gcc/nrf5x_common.ld
View file @ a55d33dd
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platform.txt
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variants/nRF52DK/pca10040.h
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