Commit c0b64a3f authored by Jim Mussared's avatar Jim Mussared Committed by Damien George

mimxrt/boards/make-pins.py: Update to use tools/boardgen.py.

Minor change to remove support for using numeric IDs for machine.Pin.  This
was previously based on the index of the pin in the board csv, but this is
different (and incompatible) with other ports.

This work was funded through GitHub Sponsors.
Signed-off-by: default avatarJim Mussared <jim.mussared@gmail.com>
parent 4d568a5b
......@@ -61,7 +61,6 @@ AF_FILE = boards/$(MCU_SERIES)_af.csv
BOARD_PINS = $(BOARD_DIR)/pins.csv
PREFIX_FILE = boards/mimxrt_prefix.c
GEN_FLEXRAM_CONFIG_SRC = $(BUILD)/flexram_config.s
GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h
GEN_PINS_HDR = $(HEADER_BUILD)/pins.h
GEN_PINS_SRC = $(BUILD)/pins_gen.c
......
......@@ -170,10 +170,6 @@
#define ENET_PHY_ADDRESS (2)
#define ENET_PHY_OPS phyksz8081_ops
// Etherner PIN definitions
#define ENET_RESET_PIN &pin_GPIO_AD_B0_04
#define ENET_INT_PIN &pin_GPIO_AD_B1_06
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1, 0xB0E9u }, \
{ IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0, 0xB0E9u }, \
......
......@@ -38,3 +38,12 @@ SD_RX,GPIO_AD_B1_05
SCK_TX,GPIO_AD_B1_01
WS_TX,GPIO_AD_B1_02
SD_TX,GPIO_AD_B1_03
-ENET_RESET,-GPIO_AD_B0_04
-ENET_INT,-GPIO_AD_B1_06
-SD_CMD,-GPIO_SD_B0_02
-SD_CLK,-GPIO_SD_B0_03
-SD_CD,-GPIO_SD_B0_06
-SD_DATA0,-GPIO_SD_B0_04
-SD_DATA1,-GPIO_SD_B0_05
-SD_DATA2,-GPIO_SD_B0_00
-SD_DATA3,-GPIO_SD_B0_01
......@@ -160,10 +160,6 @@
#define ENET_PHY_ADDRESS (2)
#define ENET_PHY_OPS phyksz8081_ops
// Etherner PIN definitions
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
......
......@@ -36,3 +36,13 @@ SD_RX,GPIO_AD_B1_12
SCK_TX,GPIO_AD_B1_14
WS_TX,GPIO_AD_B1_15
SD_TX,GPIO_AD_B1_13
-ENET_RESET,-GPIO_AD_B0_09
-ENET_INT,-GPIO_AD_B0_10
-SD_CMD,-GPIO_SD_B0_00
-SD_CLK,-GPIO_SD_B0_01
-SD_CD_B,-GPIO_B1_12
-SD_DATA0,-GPIO_SD_B0_02
-SD_DATA1,-GPIO_SD_B0_03
-SD_DATA2,-GPIO_SD_B0_04
-SD_DATA3,-GPIO_SD_B0_05
......@@ -158,10 +158,6 @@
#define ENET_PHY_ADDRESS (2)
#define ENET_PHY_OPS phyksz8081_ops
// Etherner PIN definitions
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
......
......@@ -36,3 +36,13 @@ SD_RX,GPIO_AD_B1_12
SCK_TX,GPIO_AD_B1_14
WS_TX,GPIO_AD_B1_15
SD_TX,GPIO_AD_B1_13
-ENET_RESET,-GPIO_AD_B0_09
-ENET_INT,-GPIO_AD_B0_10
-SD_CMD,-GPIO_SD_B0_00
-SD_CLK,-GPIO_SD_B0_01
-SD_CD_B,-GPIO_B1_12
-SD_DATA0,-GPIO_SD_B0_02
-SD_DATA1,-GPIO_SD_B0_03
-SD_DATA2,-GPIO_SD_B0_04
-SD_DATA3,-GPIO_SD_B0_05
......@@ -158,10 +158,6 @@
#define ENET_PHY_ADDRESS (2)
#define ENET_PHY_OPS phyksz8081_ops
// Etherner PIN definitions
#define ENET_RESET_PIN &pin_GPIO_AD_B0_09
#define ENET_INT_PIN &pin_GPIO_AD_B0_10
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
......
......@@ -36,3 +36,13 @@ SD_RX,GPIO_AD_B1_12
SCK_TX,GPIO_AD_B1_14
WS_TX,GPIO_AD_B1_15
SD_TX,GPIO_AD_B1_13
-ENET_RESET,-GPIO_AD_B0_09
-ENET_INT,-GPIO_AD_B0_10
-SD_CMD,-GPIO_SD_B0_00
-SD_CLK,-GPIO_SD_B0_01
-SD_CD_B,-GPIO_B1_12
-SD_DATA0,-GPIO_SD_B0_02
-SD_DATA1,-GPIO_SD_B0_03
-SD_DATA2,-GPIO_SD_B0_04
-SD_DATA3,-GPIO_SD_B0_05
......@@ -155,10 +155,6 @@
#define ENET_PHY KSZ8081
#define ENET_PHY_OPS phyksz8081_ops
// 10/100 Ethernet PIN definitions
#define ENET_RESET_PIN &pin_GPIO_LPSR_12
#define ENET_INT_PIN &pin_GPIO_AD_12
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00, 0, 0x06u }, \
{ IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01, 0, 0x06u }, \
......
......@@ -57,3 +57,13 @@ SD_RX,GPIO_AD_20
SCK_TX,GPIO_AD_22
WS_TX,GPIO_AD_23
SD_TX,GPIO_AD_21
-ENET_RESET,-GPIO_LPSR_12
-ENET_INT,-GPIO_AD_12
-ENET_1_RESET,-GPIO_DISP_B2_13
-SD_CMD,-GPIO_SD_B1_00
-SD_CLK,-GPIO_SD_B1_01
-SD_DATA0,-GPIO_SD_B1_02
-SD_DATA1,-GPIO_SD_B1_03
-SD_DATA2,-GPIO_SD_B1_04
-SD_DATA3,-GPIO_SD_B1_05
......@@ -127,11 +127,6 @@
#define ENET_PHY_OPS phylan8720_ops
#define ENET_TX_CLK_OUTPUT false
// Etherner PIN definitions
// No reset and interrupt pin by intention
#define ENET_RESET_PIN NULL
#define ENET_INT_PIN NULL
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
......
......@@ -9,7 +9,7 @@ J3_11,GPIO_B1_07
J3_12,GPIO_B1_09
J3_13,GPIO_B1_10
J3_14,GPIO_AD_B0_14
J3_15,GPO_AD_B0_15
J3_15,GPIO_AD_B0_15
J3_16,GPIO_AD_B1_00
J3_17,GPIO_AD_B1_01
J3_19,GPIO_AD_B0_13
......@@ -67,3 +67,13 @@ SD_RX,GPIO_AD_B1_12
SCK_TX,GPIO_AD_B1_14
WS_TX,GPIO_AD_B1_15
SD_TX,GPIO_AD_B1_13
# No ethernet reset and interrupt pin by intention
-SD_CMD,-GPIO_SD_B0_00
-SD_CLK,-GPIO_SD_B0_01
-SD_CD_B,-GPIO_B1_12
-SD_DATA0,-GPIO_SD_B0_02
-SD_DATA1,-GPIO_SD_B0_03
-SD_DATA2,-GPIO_SD_B0_04
-SD_DATA3,-GPIO_SD_B0_05
......@@ -125,10 +125,6 @@
#define ENET_PHY_ADDRESS (0)
#define ENET_PHY_OPS phydp83825_ops
// Ethernet PIN definitions
#define ENET_RESET_PIN &pin_GPIO_B0_14
#define ENET_INT_PIN &pin_GPIO_B0_15
#define IOMUX_TABLE_ENET \
{ IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0, 0xB0E9u }, \
{ IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0, 0xB0E9u }, \
......
......@@ -88,3 +88,12 @@ SD_RX,GPIO_B1_00
SCK_TX,GPIO_EMC_06
WS_TX,GPIO_EMC_05
SD_TX,GPIO_EMC_04
-ENET_RESET,-GPIO_B0_14
-ENET_INT,-GPIO_B0_15
-SD_CMD,-GPIO_SD_B0_00
-SD_CLK,-GPIO_SD_B0_01
-SD_DATA0,-GPIO_SD_B0_02
-SD_DATA1,-GPIO_SD_B0_03
-SD_DATA2,-GPIO_SD_B0_04
-SD_DATA3,-GPIO_SD_B0_05
This diff is collapsed.
......@@ -30,7 +30,7 @@
.pin = (uint32_t)(_pin), \
.muxRegister = (uint32_t)&(IOMUXC->SW_MUX_CTL_PAD[kIOMUXC_SW_MUX_CTL_PAD_##_name]), \
.configRegister = (uint32_t)&(IOMUXC->SW_PAD_CTL_PAD[kIOMUXC_SW_PAD_CTL_PAD_##_name]), \
.af_list_len = (uint8_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \
.af_list_len = MP_ARRAY_SIZE(_af_list), \
.adc_list_len = (_adc_list_len), \
.af_list = (_af_list), \
.adc_list = (_adc_list), \
......@@ -44,7 +44,7 @@
.pin = (uint32_t)(_pin), \
.muxRegister = (uint32_t)&(IOMUXC_LPSR->SW_MUX_CTL_PAD[kIOMUXC_LPSR_SW_MUX_CTL_PAD_##_name]), \
.configRegister = (uint32_t)&(IOMUXC_LPSR->SW_PAD_CTL_PAD[kIOMUXC_LPSR_SW_PAD_CTL_PAD_##_name]), \
.af_list_len = (uint8_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \
.af_list_len = MP_ARRAY_SIZE(_af_list), \
.adc_list_len = (_adc_list_len), \
.af_list = (_af_list), \
.adc_list = (_adc_list), \
......@@ -58,7 +58,7 @@
.pin = (uint32_t)(_pin), \
.muxRegister = (uint32_t)&(IOMUXC_SNVS->SW_MUX_CTL_PAD_##_name), \
.configRegister = (uint32_t)&(IOMUXC_SNVS->SW_PAD_CTL_PAD_##_name), \
.af_list_len = (uint8_t)(sizeof((_af_list)) / sizeof(machine_pin_af_obj_t)), \
.af_list_len = MP_ARRAY_SIZE(_af_list), \
.adc_list_len = (_adc_list_len), \
.af_list = (_af_list), \
.adc_list = (_adc_list), \
......
......@@ -365,7 +365,15 @@ void eth_init_0(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
uint32_t source_clock = eth_clock_init(eth_id, phy_clock);
eth_gpio_init(iomux_table_enet, ARRAY_SIZE(iomux_table_enet), ENET_RESET_PIN, ENET_INT_PIN);
const machine_pin_obj_t *reset_pin = NULL;
#if defined(pin_ENET_RESET)
reset_pin = pin_ENET_RESET;
#endif
const machine_pin_obj_t *int_pin = NULL;
#if defined(pin_ENET_INT)
int_pin = pin_ENET_INT;
#endif
eth_gpio_init(iomux_table_enet, ARRAY_SIZE(iomux_table_enet), reset_pin, int_pin);
mp_hal_get_mac(0, hw_addr);
......@@ -411,7 +419,15 @@ void eth_init_1(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
uint32_t source_clock = eth_clock_init(eth_id, phy_clock);
eth_gpio_init(iomux_table_enet_1, ARRAY_SIZE(iomux_table_enet_1), ENET_1_RESET_PIN, ENET_1_INT_PIN);
const machine_pin_obj_t *reset_pin = NULL;
#if defined(pin_ENET_1_INT)
reset_pin = pin_ENET_1_RESET;
#endif
const machine_pin_obj_t *int_pin = NULL;
#if defined(pin_ENET_1_INT)
int_pin = pin_ENET_1_INT;
#endif
eth_gpio_init(iomux_table_enet_1, ARRAY_SIZE(iomux_table_enet_1), reset_pin, int_pin);
#if defined MIMXRT117x_SERIES
NVIC_SetPriority(ENET_1G_MAC0_Tx_Rx_1_IRQn, IRQ_PRI_PENDSV);
......
......@@ -34,13 +34,13 @@
#if defined(MICROPY_HW_LED1_PIN)
const machine_led_obj_t machine_led_obj[] = {
{ .base = {&machine_led_type}, .led_id = 1U, .led_pin = &MICROPY_HW_LED1_PIN, },
{ .base = {&machine_led_type}, .led_id = 1U, .led_pin = MICROPY_HW_LED1_PIN, },
#if defined(MICROPY_HW_LED2_PIN)
{ .base = {&machine_led_type}, .led_id = 2U, .led_pin = &MICROPY_HW_LED2_PIN, },
{ .base = {&machine_led_type}, .led_id = 2U, .led_pin = MICROPY_HW_LED2_PIN, },
#if defined(MICROPY_HW_LED3_PIN)
{ .base = {&machine_led_type}, .led_id = 3U, .led_pin = &MICROPY_HW_LED3_PIN, },
{ .base = {&machine_led_type}, .led_id = 3U, .led_pin = MICROPY_HW_LED3_PIN, },
#if defined(MICROPY_HW_LED4_PIN)
{ .base = {&machine_led_type}, .led_id = 4U, .led_pin = &MICROPY_HW_LED4_PIN, },
{ .base = {&machine_led_type}, .led_id = 4U, .led_pin = MICROPY_HW_LED4_PIN, },
#endif
#endif
#endif
......
......@@ -191,8 +191,9 @@ STATIC const machine_pin_af_obj_t *af_name_decode_qtmr(const machine_pin_af_obj_
#endif
STATIC bool is_board_pin(const machine_pin_obj_t *pin) {
for (int i = 0; i < num_board_pins; i++) {
if (pin == machine_pin_board_pins[i]) {
const mp_map_t *board_map = &machine_pin_board_pins_locals_dict.map;
for (uint i = 0; i < board_map->alloc; i++) {
if (pin == MP_OBJ_TO_PTR(board_map->table[i].value)) {
return true;
}
}
......
......@@ -152,14 +152,6 @@ const machine_pin_obj_t *pin_find(mp_obj_t user_obj) {
return pin_obj;
}
// If pin is SMALL_INT
if (mp_obj_is_small_int(user_obj)) {
uint8_t value = MP_OBJ_SMALL_INT_VALUE(user_obj);
if (value < num_board_pins) {
return machine_pin_board_pins[value];
}
}
// See if the pin name matches a board pin
pin_obj = pin_find_named_pin(&machine_pin_board_pins_locals_dict, user_obj);
if (pin_obj) {
......
......@@ -147,9 +147,6 @@ extern const mp_obj_type_t machine_pin_af_type;
// Include board specific pins
#include "genhdr/pins.h" // pins.h must included at this location
extern const machine_pin_obj_t *machine_pin_board_pins[];
extern const uint32_t num_board_pins;
extern const mp_obj_type_t machine_pin_board_pins_obj_type;
extern const mp_obj_type_t machine_pin_cpu_pins_obj_type;
......
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