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xpstem
micropython
Commits
70a6a15f
Commit
70a6a15f
authored
Apr 14, 2018
by
iabdalkader
Committed by
Damien George
Apr 23, 2018
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stm32/rng: Set RNG clock source for STM32H7.
parent
bdff68db
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ports/stm32/rng.c
ports/stm32/rng.c
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ports/stm32/rng.c
View file @
70a6a15f
...
...
@@ -33,6 +33,11 @@
uint32_t
rng_get
(
void
)
{
// Enable the RNG peripheral if it's not already enabled
if
(
!
(
RNG
->
CR
&
RNG_CR_RNGEN
))
{
#if defined(STM32H7)
// Set RNG Clock source
__HAL_RCC_PLLCLKOUT_ENABLE
(
RCC_PLL1_DIVQ
);
__HAL_RCC_RNG_CONFIG
(
RCC_RNGCLKSOURCE_PLL
);
#endif
__HAL_RCC_RNG_CLK_ENABLE
();
RNG
->
CR
|=
RNG_CR_RNGEN
;
}
...
...
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