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Commit 00963a4e authored by Damien George's avatar Damien George
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stm32/powerctrl: Allow a board to configure AHB and APB clock dividers. 

Signed-off-by: default avatarDamien George <damien@micropython.org>
parent a66286f3
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Showing with 38 additions and 19 deletions
ports/stm32/mpconfigboard_common.h
View file @ 00963a4e
...@@ -310,6 +310,25 @@ ...@@ -310,6 +310,25 @@
#endif #endif
#endif #endif
// Configure the default bus clock divider values
#ifndef MICROPY_HW_CLK_AHB_DIV
#if defined(STM32H7)
#define MICROPY_HW_CLK_AHB_DIV (RCC_HCLK_DIV2)
#define MICROPY_HW_CLK_APB1_DIV (RCC_APB1_DIV2)
#define MICROPY_HW_CLK_APB2_DIV (RCC_APB2_DIV2)
#define MICROPY_HW_CLK_APB3_DIV (RCC_APB3_DIV2)
#define MICROPY_HW_CLK_APB4_DIV (RCC_APB4_DIV2)
#elif defined(STM32L4)
#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1)
#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV1)
#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV1)
#else
#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1)
#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV4)
#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV2)
#endif
#endif
// If disabled then try normal (non-bypass) LSE first, with fallback to LSI. // If disabled then try normal (non-bypass) LSE first, with fallback to LSI.
// If enabled first try LSE in bypass mode. If that fails to start, try non-bypass mode, with fallback to LSI. // If enabled first try LSE in bypass mode. If that fails to start, try non-bypass mode, with fallback to LSI.
#ifndef MICROPY_HW_RTC_USE_BYPASS #ifndef MICROPY_HW_RTC_USE_BYPASS
......
ports/stm32/powerctrl.c
View file @ 00963a4e
...@@ -377,8 +377,8 @@ set_clk: ...@@ -377,8 +377,8 @@ set_clk:
RCC_ClkInitStruct.APB2CLKDivider = calc_apb2_div(ahb / apb2); RCC_ClkInitStruct.APB2CLKDivider = calc_apb2_div(ahb / apb2);
#if defined(STM32H7) #if defined(STM32H7)
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB3CLKDivider = MICROPY_HW_CLK_APB3_DIV;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; RCC_ClkInitStruct.APB4CLKDivider = MICROPY_HW_CLK_APB4_DIV;
#endif #endif
#if MICROPY_HW_CLK_LAST_FREQ #if MICROPY_HW_CLK_LAST_FREQ
......
ports/stm32/system_stm32.c
View file @ 00963a4e
...@@ -272,9 +272,9 @@ void SystemClock_Config(void) { ...@@ -272,9 +272,9 @@ void SystemClock_Config(void) {
n = MICROPY_HW_CLK_PLLN; n = MICROPY_HW_CLK_PLLN;
p = MICROPY_HW_CLK_PLLP; p = MICROPY_HW_CLK_PLLP;
q = MICROPY_HW_CLK_PLLQ; q = MICROPY_HW_CLK_PLLQ;
h = RCC_SYSCLK_DIV1; h = MICROPY_HW_CLK_AHB_DIV;
b1 = RCC_HCLK_DIV4; b1 = MICROPY_HW_CLK_APB1_DIV;
b2 = RCC_HCLK_DIV2; b2 = MICROPY_HW_CLK_APB2_DIV;
} else { } else {
h <<= 4; h <<= 4;
b1 <<= 10; b1 <<= 10;
...@@ -285,9 +285,9 @@ void SystemClock_Config(void) { ...@@ -285,9 +285,9 @@ void SystemClock_Config(void) {
RCC_OscInitStruct.PLL.PLLP = p; // MICROPY_HW_CLK_PLLP; RCC_OscInitStruct.PLL.PLLP = p; // MICROPY_HW_CLK_PLLP;
RCC_OscInitStruct.PLL.PLLQ = q; // MICROPY_HW_CLK_PLLQ; RCC_OscInitStruct.PLL.PLLQ = q; // MICROPY_HW_CLK_PLLQ;
RCC_ClkInitStruct.AHBCLKDivider = h; // RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = h;
RCC_ClkInitStruct.APB1CLKDivider = b1; // RCC_HCLK_DIV4; RCC_ClkInitStruct.APB1CLKDivider = b1;
RCC_ClkInitStruct.APB2CLKDivider = b2; // RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = b2;
#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ #else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM; RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN; RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
...@@ -304,20 +304,20 @@ void SystemClock_Config(void) { ...@@ -304,20 +304,20 @@ void SystemClock_Config(void) {
#endif #endif
#if defined(STM32F4) || defined(STM32F7) #if defined(STM32F4) || defined(STM32F7)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV;
#elif defined(STM32L4) #elif defined(STM32L4)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV;
#elif defined(STM32H7) #elif defined(STM32H7)
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB3CLKDivider = MICROPY_HW_CLK_APB3_DIV;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; RCC_ClkInitStruct.APB4CLKDivider = MICROPY_HW_CLK_APB4_DIV;
#endif #endif
#endif #endif
......
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