1. 10 May, 2022 2 commits
  2. 08 May, 2022 2 commits
  3. 05 May, 2022 3 commits
  4. 04 May, 2022 1 commit
  5. 01 May, 2022 1 commit
  6. 28 Apr, 2022 2 commits
  7. 27 Apr, 2022 5 commits
  8. 26 Apr, 2022 2 commits
  9. 25 Apr, 2022 4 commits
    • Andy2No's avatar
      Update SimpleTone.ino (#552) · 797abb5a
      Andy2No authored
      Adds code to define which pins are used, moving them from the defaults, which are the same as the only three analogue input pins, and adding comments to explain how to change them.
      
      The original didn't give any clues about which pins were used, which isn't ideal for a beginner - it was necessary to look at the code for the library, to work that out.
      
      The new code redundantly defines a pWS pin number (as pBCLK+1), which isn't used in the example, but is meant as a reminder to the person using it, of how to wire up WS.
      797abb5a
    • Earle F. Philhower, III's avatar
    • Earle F. Philhower, III's avatar
    • Earle F. Philhower, III's avatar
      Add FreeRTOS support thanks to @hfellner (#533) · bda630e4
      Earle F. Philhower, III authored
      Using all the work from @hfellner and others, add FreeRTOS
      SMP support.
      
      Allow idling cores through the FreeRTOS FIFO queue to
      allow for file system and EEPROM support.
      
      Make delay a weak function so FreeRTOS can override.
      
      Add cycle count support under FreeRTOS using a PIO SM.
      
      Use a task-based approach for handling the USB periodic work
      instead of the IRQ-based one in the main core.
      
      Set 8 prio levels so it fits in 3 bits nicely (0..7).
      bda630e4
  10. 24 Apr, 2022 3 commits
  11. 22 Apr, 2022 3 commits
  12. 17 Apr, 2022 2 commits
  13. 16 Apr, 2022 1 commit
  14. 10 Apr, 2022 1 commit
  15. 09 Apr, 2022 1 commit
  16. 30 Mar, 2022 1 commit
  17. 29 Mar, 2022 1 commit
  18. 17 Mar, 2022 1 commit
  19. 16 Mar, 2022 2 commits
    • randomllama's avatar
    • Earle F. Philhower, III's avatar
      Avoid "chunkiness" of UART FIFO availability (#511) · 53043830
      Earle F. Philhower, III authored
      * Avoid "chunkiness" of UART FIFO availability
      
      The UART FIFO will generate an IRQ to transfer data into the SerialUART
      FIFOs either every 4 received bytes, or every 4 idle byte times.  This
      causes the ::available count to report "0" until either of those two
      cases happen, causing a potentially delay in data becoming available to
      the app.
      
      Change the code to pull data from the HW FIFO on a read/available/peek.
      Use a non-blocking mutex and IRQ disabling to safely empty the FIFO from
      user space.  The mutex added to the IRQ is non-blocking and will be
      a single CAS the vast majority of the time, so it should not impact the
      Serial performance.
      
      Fixes #464 and others where `setPollingMode()` was needed as a workaround.
      
      Make sure we have all mutexes locked before we disable the port and free
      the queue to avoid evil cases.
      
      Only init the mutexes once, on object creation.
      
      In polled mode, don't bother acquiring/releasing the fifo mutex.
      
      When begin() is called on an already running port, call end() to clean
      up the old data/etc. before making a new queue/config.  This avoids a
      memory leak and potential write-after-free case.
      53043830
  20. 14 Mar, 2022 1 commit
  21. 06 Mar, 2022 1 commit