fix(esp): Fix getFlashChipMode breaking on S3 and C3 (#9758)

ffeebf8d · Me No Dev · GitHub · e33022f3 · ffeebf8d · ffeebf8d
Unverified Commit ffeebf8d authored Jun 03, 2024 by Me No Dev Committed by GitHub Jun 03, 2024
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Showing with 6 additions and 4 deletions

cores/esp32/Esp.cpp cores/esp32/Esp.cpp +3 -2

cores/esp32/chip-debug-report.cpp cores/esp32/chip-debug-report.cpp +3 -2

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--- a/cores/esp32/Esp.cpp
+++ b/cores/esp32/Esp.cpp
@@ -71,9 +71,10 @@ extern "C" {
 // REG_SPI_BASE is not defined for S3/C3 ??

 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
-#ifndef REG_SPI_BASE
-#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
+#ifdef REG_SPI_BASE
+#undef REG_SPI_BASE
 #endif  // REG_SPI_BASE
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
 #endif  // TARGET

 /**

--- a/cores/esp32/chip-debug-report.cpp
+++ b/cores/esp32/chip-debug-report.cpp
@@ -113,9 +113,10 @@ static void printFlashInfo(void) {
 #endif
 // REG_SPI_BASE is not defined for S3/C3 ??
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
-#ifndef REG_SPI_BASE
-#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
+#ifdef REG_SPI_BASE
+#undef REG_SPI_BASE
 #endif  // REG_SPI_BASE
+#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i) > 1) ? (((i) * 0x1000) + 0x20000) : (((~(i)) & 1) * 0x1000)))
 #endif  // TARGET

  chip_report_printf("Flash Info:\n");