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xpstem
TFT_eSPI
Commits
f71df4ff
Commit
f71df4ff
authored
Mar 25, 2020
by
Bodmer
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#581 fallout update
parent
d1b0bab9
Changes
2
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2 changed files
with
254 additions
and
238 deletions
+254
-238
Processors/TFT_eSPI_STM32.c
Processors/TFT_eSPI_STM32.c
+16
-16
Processors/TFT_eSPI_STM32.h
Processors/TFT_eSPI_STM32.h
+238
-222
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Processors/TFT_eSPI_STM32.c
View file @
f71df4ff
...
...
@@ -132,24 +132,24 @@ void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
// Now we can use a minimal set of register changes
if
(
mode
==
OUTPUT
)
{
LL_GPIO_SetPinMode
(
D0_PIN_PORT
,
D0_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D1_PIN_PORT
,
D1_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D2_PIN_PORT
,
D2_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D3_PIN_PORT
,
D3_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D4_PIN_PORT
,
D4_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D5_PIN_PORT
,
D5_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D6_PIN_PORT
,
D6_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D7_PIN_PORT
,
D7_PIN_
BIT
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D0_PIN_PORT
,
D0_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D1_PIN_PORT
,
D1_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D2_PIN_PORT
,
D2_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D3_PIN_PORT
,
D3_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D4_PIN_PORT
,
D4_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D5_PIN_PORT
,
D5_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D6_PIN_PORT
,
D6_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
LL_GPIO_SetPinMode
(
D7_PIN_PORT
,
D7_PIN_
MASK
,
LL_GPIO_MODE_OUTPUT
);
}
else
{
LL_GPIO_SetPinMode
(
D0_PIN_PORT
,
D0_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D1_PIN_PORT
,
D1_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D2_PIN_PORT
,
D2_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D3_PIN_PORT
,
D3_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D4_PIN_PORT
,
D4_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D5_PIN_PORT
,
D5_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D6_PIN_PORT
,
D6_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D7_PIN_PORT
,
D7_PIN_
BIT
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D0_PIN_PORT
,
D0_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D1_PIN_PORT
,
D1_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D2_PIN_PORT
,
D2_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D3_PIN_PORT
,
D3_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D4_PIN_PORT
,
D4_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D5_PIN_PORT
,
D5_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D6_PIN_PORT
,
D6_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
LL_GPIO_SetPinMode
(
D7_PIN_PORT
,
D7_PIN_
MASK
,
LL_GPIO_MODE_INPUT
);
}
}
...
...
Processors/TFT_eSPI_STM32.h
View file @
f71df4ff
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