Commit f0ec6d22 authored by Bodmer's avatar Bodmer

Add ESP32 C3 support

Tested with Stamp C3
parent 18a76f1c
......@@ -142,7 +142,6 @@ void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
pinMode(TFT_D5, mode);
pinMode(TFT_D6, mode);
pinMode(TFT_D7, mode);
return;
}
/***************************************************************************************
......
......@@ -144,7 +144,6 @@ void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
pinMode(TFT_D5, mode);
pinMode(TFT_D6, mode);
pinMode(TFT_D7, mode);
return;
}
/***************************************************************************************
......
......@@ -2,6 +2,8 @@
// TFT_eSPI driver functions for ESP32 processors //
////////////////////////////////////////////////////
// Temporarily a separate file to TFT_eSPI_ESP32.h until board package low level API stabilises
#ifndef _TFT_eSPI_ESP32H_
#define _TFT_eSPI_ESP32H_
......@@ -22,15 +24,11 @@
#define VSPI FSPI
#endif
// Fix IDF problems with ESP32C3
#if CONFIG_IDF_TARGET_ESP32C3
// Fix ESP32C3 IDF bug for missing definition (VSPI/FSPI only tested at the moment)
#ifndef REG_SPI_BASE
//Will this work as per S3? #define REG_SPI_BASE(i) (((i)>1) ? (DR_REG_SPI3_BASE) : (DR_REG_SPI2_BASE))
#define REG_SPI_BASE(i) (DR_REG_SPI1_BASE + (((i)>1) ? (((i)* 0x1000) + 0x20000) : (((~(i)) & 1)* 0x1000 )))
#define REG_SPI_BASE(i) DR_REG_SPI2_BASE
#endif
// Fix ESP32C3 IDF bug for name change
......@@ -53,12 +51,12 @@ VSPI = 3, uses SPI3
ESP32-S2:
FSPI = 1, uses SPI2
HSPI = 2, uses SPI3
VSPI not defined
VSPI not defined so have made VSPI = HSPI
ESP32 C3:
FSPI = 0, uses SPI2 ???? To be checked
HSPI = 1, uses SPI3 ???? To be checked
VSPI not defined
ESP32 C3: Only 1 SPI port available
FSPI = 1, uses SPI2
HSPI = 1, uses SPI2
VSPI not defined so have made VSPI = HSPI
For ESP32/S2/C3:
SPI1_HOST = 0
......@@ -66,24 +64,8 @@ SPI2_HOST = 1
SPI3_HOST = 2
*/
// ESP32 specific SPI port selection
#ifdef USE_HSPI_PORT
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_PORT HSPI //HSPI is port 2 on ESP32
#else
#define SPI_PORT 3 //HSPI is port 3 on ESP32 S2
#endif
#elif defined(USE_FSPI_PORT)
#define SPI_PORT 2 //FSPI(ESP32 S2)
#else
#ifdef CONFIG_IDF_TARGET_ESP32
#define SPI_PORT VSPI
#elif CONFIG_IDF_TARGET_ESP32S2
#define SPI_PORT 2 //FSPI(ESP32 S2)
#elif CONFIG_IDF_TARGET_ESP32C3
#define SPI_PORT FSPI
#endif
#endif
// ESP32 specific SPI port selection - only SPI2_HOST available on C3
#define SPI_PORT SPI2_HOST
#ifdef RPI_DISPLAY_TYPE
#define CMD_BITS (16-1)
......@@ -568,13 +550,13 @@ SPI3_HOST = 2
#define tft_Write_16N(C) *_spi_mosi_dlen = 16-1; \
*_spi_w = ((C)<<8 | (C)>>8); \
*_spi_cmd = SPI_USR;
#else
#else
#define tft_Write_16N(C) *_spi_mosi_dlen = 16-1; \
*_spi_w = ((C)<<8 | (C)>>8); \
*_spi_cmd = SPI_UPDATE; \
while (*_spi_cmd & SPI_UPDATE); \
*_spi_cmd = SPI_USR;
#endif
#endif
// Write 16 bits
#define tft_Write_16S(C) TFT_WRITE_BITS(C, 16)
......
......@@ -144,7 +144,6 @@ void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
pinMode(TFT_D5, mode);
pinMode(TFT_D6, mode);
pinMode(TFT_D7, mode);
return;
}
/***************************************************************************************
......
......@@ -16,7 +16,7 @@
#ifndef _TFT_eSPIH_
#define _TFT_eSPIH_
#define TFT_ESPI_VERSION "2.4.60"
#define TFT_ESPI_VERSION "2.4.61"
// Bit level feature flags
// Bit 0 set: viewport capability
......
......@@ -83,7 +83,9 @@
//#include <User_Setups/Setup61_RP2040_ILI9341_PIO_SPI.h> // Setup file for RP2040 with PIO SPI ILI9341
//#include <User_Setups/Setup62_RP2040_Nano_Connect_ILI9341.h> // Setup file for RP2040 with SPI ILI9341
//#include <User_Setups/Setup70_ESP32_S2_ILI9341.h> // Setup file for ESP32 S2 with SPI ILI9341
//#include <User_Setups/Setup70_ESP32_S2_ILI9341.h> // Setup file for ESP32 S2 with SPI ILI9341
//#include <User_Setups/Setup70b_ESP32_S3_ILI9341.h> // Setup file for ESP32 S3 with SPI ILI9341
//#include <User_Setups/Setup70c_ESP32_C3_ILI9341.h> // Setup file for ESP32 C3 with SPI ILI9341
//#include <User_Setups/Setup71_ESP32_S2_ST7789.h> // Setup file for ESP32 S2 with ST7789
//#include <User_Setups/Setup72_ESP32_ST7789_172x320.h> // Setup file for ESP32 with ST7789 1.47" 172x320
......
// Setup for the ESP32 C3 with ILI9341 display
// Note SPI DMA with ESP32 C3 is not currently supported
#define USER_SETUP_ID 70
// See SetupX_Template.h for all options available
#define ILI9341_DRIVER
//#define ST7796_DRIVER
//#define ILI9488_DRIVER
// Adafruit qtpy default
//TFT_CS 6
//TFT_MOSI 7
//TFT_MISO 8
//TFT_SCLK 10
// Lolin C3 mini default
//TFT_CS 5
//TFT_MOSI 4
//TFT_MISO 3
//TFT_SCLK 2
//ESP32 C3 generic default
//TFT_CS 7
//TFT_MOSI 6
//TFT_MISO 5
//TFT_SCLK 4
#define TFT_CS 7
#define TFT_MOSI 6
#define TFT_MISO 5
#define TFT_SCLK 4
#define TFT_DC 8
#define TFT_RST 10
//#define TOUCH_CS 1 // Optional for touch screen
#define LOAD_GLCD
#define LOAD_FONT2
#define LOAD_FONT4
#define LOAD_FONT6
#define LOAD_FONT7
#define LOAD_FONT8
#define LOAD_GFXFF
#define SMOOTH_FONT
//#define SPI_FREQUENCY 27000000
#define SPI_FREQUENCY 40000000 // Maximum for ILI9341
#define SPI_READ_FREQUENCY 6000000 // 6 MHz is the maximum SPI read speed for the ST7789V
#define SPI_TOUCH_FREQUENCY 2500000
{
"name": "TFT_eSPI",
"version": "2.4.60",
"version": "2.4.61",
"keywords": "Arduino, tft, display, ttgo, LilyPi, WT32-SC01, ePaper, display, Pico, RP2040 Nano Connect, RP2040, STM32, ESP8266, NodeMCU, ESP32, M5Stack, ILI9341, ST7735, ILI9163, S6D02A1, ILI9481, ILI9486, ILI9488, ST7789, ST7796, RM68140, SSD1351, SSD1963, ILI9225, HX8357D, GC9A01, R61581",
"description": "A TFT and ePaper SPI graphics library with optimisation for Raspberry Pi Pico, RP2040, ESP8266, ESP32 and STM32",
"repository":
......
name=TFT_eSPI
version=2.4.60
version=2.4.61
author=Bodmer
maintainer=Bodmer
sentence=TFT graphics library for Arduino processors with performance optimisation for RP2040, STM32, ESP8266 and ESP32
......
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