Update for high GPIO

Processors/TFT_eSPI_ESP32_S3.c

@@ -96,21 +96,20 @@ uint8_t TFT_eSPI::readByte(void)
 
 #if defined (TFT_PARALLEL_8_BIT)
   RD_L;
-  uint32_t reg;           // Read all GPIO pins 0-31
-  reg = gpio_input_get(); // Read three times to allow for bus access time
-  reg = gpio_input_get();
-  reg = gpio_input_get(); // Data should be stable now
+  b  = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Read three times to allow for bus access time
+  b  = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET));
+  b  = gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)); // Data should be stable now
   RD_H;
 
   // Check GPIO bits used and build value
-  b  = (((reg>>TFT_D0)&1) << 0);
-  b |= (((reg>>TFT_D1)&1) << 1);
-  b |= (((reg>>TFT_D2)&1) << 2);
-  b |= (((reg>>TFT_D3)&1) << 3);
-  b |= (((reg>>TFT_D4)&1) << 4);
-  b |= (((reg>>TFT_D5)&1) << 5);
-  b |= (((reg>>TFT_D6)&1) << 6);
-  b |= (((reg>>TFT_D7)&1) << 7);
+  b  = (gpio_get_level((gpio_num_t)(TFT_D0-MASK_OFFSET)) << 0);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D1-MASK_OFFSET)) << 1);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D2-MASK_OFFSET)) << 2);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D3-MASK_OFFSET)) << 3);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D4-MASK_OFFSET)) << 4);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D5-MASK_OFFSET)) << 5);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D6-MASK_OFFSET)) << 6);
+  b |= (gpio_get_level((gpio_num_t)(TFT_D7-MASK_OFFSET)) << 7);
 #endif
 
   return b;