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TFT_eSPI
Unverified Commit 168a73fe authored by Bodmer's avatar Bodmer Committed by GitHub
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Merge pull request #1143 from Bodmer/STM32_Port_D_test 

Add Port C and D option for 8 bit parallel on STM32 processors
parents f96efe5d add47960
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Showing with 63 additions and 72 deletions
Processors/TFT_eSPI_STM32.c
View file @ 168a73fe
......@@ -84,7 +84,7 @@ void TFT_eSPI::end_SDA_Read(void)
** Description: Write a block of pixels of the same colour
***************************************************************************************/
void TFT_eSPI::pushBlock(uint16_t color, uint32_t len){
// Loop unrolling improves speed dramtically graphics test 0.634s => 0.374s
// Loop unrolling improves speed dramatically graphics test 0.634s => 0.374s
while (len>31) {
#if !defined (SSD1963_DRIVER)
// 32D macro writes 16 bits twice
......@@ -165,6 +165,22 @@ void TFT_eSPI::busDir(uint32_t mask, uint8_t mode)
if (mode == OUTPUT) GPIOB->MODER = (GPIOB->MODER & 0xFFFF0000) | 0x00005555;
else GPIOB->MODER &= 0xFFFF0000;
#endif
#elif defined (STM_PORTC_DATA_BUS)
#if defined (STM32F1xx)
if (mode == OUTPUT) GPIOC->CRL = 0x33333333;
else GPIOC->CRL = 0x88888888;
#else
if (mode == OUTPUT) GPIOC->MODER = (GPIOC->MODER & 0xFFFF0000) | 0x00005555;
else GPIOC->MODER &= 0xFFFF0000;
#endif
#elif defined (STM_PORTD_DATA_BUS)
#if defined (STM32F1xx)
if (mode == OUTPUT) GPIOD->CRL = 0x33333333;
else GPIOD->CRL = 0x88888888;
#else
if (mode == OUTPUT) GPIOD->MODER = (GPIOD->MODER & 0xFFFF0000) | 0x00005555;
else GPIOD->MODER &= 0xFFFF0000;
#endif
#else
if (mode == OUTPUT) {
LL_GPIO_SetPinMode(D0_PIN_PORT, D0_PIN_MASK, LL_GPIO_MODE_OUTPUT);
......@@ -222,6 +238,16 @@ uint8_t TFT_eSPI::readByte(void)
b = GPIOB->IDR;
b = GPIOB->IDR;
b = (GPIOB->IDR) & 0xFF;
#elif defined (STM_PORTC_DATA_BUS)
b = GPIOC->IDR;
b = GPIOC->IDR;
b = GPIOC->IDR;
b = (GPIOC->IDR) & 0xFF;
#elif defined (STM_PORTD_DATA_BUS)
b = GPIOD->IDR;
b = GPIOD->IDR;
b = GPIOD->IDR;
b = (GPIOD->IDR) & 0xFF;
#else
b = RD_TFT_D0 | RD_TFT_D0 | RD_TFT_D0 | RD_TFT_D0; //Delay for bits to settle
......
Processors/TFT_eSPI_STM32.h
View file @ 168a73fe
......@@ -723,77 +723,42 @@
// Support for other STM32 boards (not optimised!)
////////////////////////////////////////////////////////////////////////////////////////
#else
#if defined (STM_PORTA_DATA_BUS)
#if defined (STM_PORTA_DATA_BUS) || defined (STM_PORTB_DATA_BUS) || defined (STM_PORTC_DATA_BUS) || defined (STM_PORTD_DATA_BUS)
#if defined (STM_PORTA_DATA_BUS)
#define GPIOX GPIOA
#elif defined (STM_PORTB_DATA_BUS)
#define GPIOX GPIOB
#elif defined (STM_PORTC_DATA_BUS)
#define GPIOX GPIOC
#elif defined (STM_PORTD_DATA_BUS)
#define GPIOX GPIOD
#endif
// Write 8 bits to TFT
#define tft_Write_8(C) GPIOA->BSRR = (0x00FF0000 | (uint8_t)(C)); WR_L; WR_STB
#define tft_Write_8(C) GPIOX->BSRR = (0x00FF0000 | (uint8_t)(C)); WR_L; WR_STB
#if defined (SSD1963_DRIVER)
// Write 18 bit color to TFT (untested)
uint8_t r6, g6, b6;
#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
GPIOA->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \
GPIOA->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \
GPIOA->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB
// 18 bit color write with swapped bytes
#define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap)
#else
// Write 16 bits to TFT
#define tft_Write_16(C) GPIOA->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB; \
GPIOA->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB
// 16 bit write with swapped bytes
#define tft_Write_16S(C) GPIOA->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB; \
GPIOA->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB
#endif
#define tft_Write_32(C) tft_Write_16((uint16_t)((C)>>16)); tft_Write_16((uint16_t)(C))
#if defined (SSD1963_DRIVER)
#define tft_Write_32C(C,D) tft_Write_16((uint16_t)(C)); tft_Write_16((uint16_t)(D))
// Write 18 bit color to TFT (untested)
uint8_t r6, g6, b6;
#define tft_Write_16(C) r6 = (((C) & 0xF800)>> 8); g6 = (((C) & 0x07E0)>> 3); b6 = (((C) & 0x001F)<< 3); \
GPIOX->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \
GPIOX->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \
GPIOX->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB
#define tft_Write_32D(C) tft_Write_16((uint16_t)(C)); tft_Write_16((uint16_t)(C))
// 18 bit color write with swapped bytes
#define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap)
// Read a data bit
#define RD_TFT_D0 ((GPIOA->IDR) & 0x01) // Read pin TFT_D0
#define RD_TFT_D1 ((GPIOA->IDR) & 0x02) // Read pin TFT_D1
#define RD_TFT_D2 ((GPIOA->IDR) & 0x04) // Read pin TFT_D2
#define RD_TFT_D3 ((GPIOA->IDR) & 0x08) // Read pin TFT_D3
#define RD_TFT_D4 ((GPIOA->IDR) & 0x10) // Read pin TFT_D4
#define RD_TFT_D5 ((GPIOA->IDR) & 0x20) // Read pin TFT_D5
#define RD_TFT_D6 ((GPIOA->IDR) & 0x40) // Read pin TFT_D6
#define RD_TFT_D7 ((GPIOA->IDR) & 0x80) // Read pin TFT_D7
#elif defined (STM_PORTB_DATA_BUS)
// Write 8 bits to TFT
#define tft_Write_8(C) GPIOB->BSRR = (0x00FF0000 | (uint8_t)(C)); WR_L; WR_STB
#else
#if defined (SSD1963_DRIVER)
// Write 18 bit color to TFT (untested)
uint8_t r, g, b;
#define tft_Write_16(C) uint8_t r = (((C) & 0xF800)>> 8); uint8_t g = (((C) & 0x07E0)>> 3); uint8_t b = (((C) & 0x001F)<< 3); \
GPIOB->BSRR = (0x00FF0000 | (uint8_t)(r6)); WR_L; WR_STB; \
GPIOB->BSRR = (0x00FF0000 | (uint8_t)(g6)); WR_L; WR_STB; \
GPIOB->BSRR = (0x00FF0000 | (uint8_t)(b6)); WR_L; WR_STB
// Write 16 bits to TFT
#define tft_Write_16(C) GPIOX->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB; \
GPIOX->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB
// 18 bit color write with swapped bytes
#define tft_Write_16S(C) uint16_t Cswap = ((C) >>8 | (C) << 8); tft_Write_16(Cswap)
#else
// Write 16 bits to TFT
#define tft_Write_16(C) GPIOB->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB; \
GPIOB->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB
// 16 bit write with swapped bytes
#define tft_Write_16S(C) GPIOB->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB; \
GPIOB->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB
#endif
// 16 bit write with swapped bytes
#define tft_Write_16S(C) GPIOX->BSRR = (0x00FF0000 | (uint8_t)(C>>0)); WR_L; WR_STB; \
GPIOX->BSRR = (0x00FF0000 | (uint8_t)(C>>8)); WR_L; WR_STB
#endif
#define tft_Write_32(C) tft_Write_16((uint16_t)((C)>>16)); tft_Write_16((uint16_t)(C))
......@@ -802,14 +767,14 @@
#define tft_Write_32D(C) tft_Write_16((uint16_t)(C)); tft_Write_16((uint16_t)(C))
// Read a data bit
#define RD_TFT_D0 ((GPIOB->IDR) & 0x80) // Read pin TFT_D0
#define RD_TFT_D1 ((GPIOB->IDR) & 0x40) // Read pin TFT_D1
#define RD_TFT_D2 ((GPIOB->IDR) & 0x20) // Read pin TFT_D2
#define RD_TFT_D3 ((GPIOB->IDR) & 0x10) // Read pin TFT_D3
#define RD_TFT_D4 ((GPIOB->IDR) & 0x08) // Read pin TFT_D4
#define RD_TFT_D5 ((GPIOB->IDR) & 0x04) // Read pin TFT_D5
#define RD_TFT_D6 ((GPIOB->IDR) & 0x02) // Read pin TFT_D6
#define RD_TFT_D7 ((GPIOB->IDR) & 0x01) // Read pin TFT_D7
#define RD_TFT_D0 ((GPIOX->IDR) & 0x01) // Read pin TFT_D0
#define RD_TFT_D1 ((GPIOX->IDR) & 0x02) // Read pin TFT_D1
#define RD_TFT_D2 ((GPIOX->IDR) & 0x04) // Read pin TFT_D2
#define RD_TFT_D3 ((GPIOX->IDR) & 0x08) // Read pin TFT_D3
#define RD_TFT_D4 ((GPIOX->IDR) & 0x10) // Read pin TFT_D4
#define RD_TFT_D5 ((GPIOX->IDR) & 0x20) // Read pin TFT_D5
#define RD_TFT_D6 ((GPIOX->IDR) & 0x40) // Read pin TFT_D6
#define RD_TFT_D7 ((GPIOX->IDR) & 0x80) // Read pin TFT_D7
#else
// This will work with any STM32 to parallel TFT pin mapping but will be slower
......
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