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xpstem
RF24
Commits
f8791b1d
Commit
f8791b1d
authored
Oct 06, 2014
by
TMRh20
Browse files
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Merge remote-tracking branch 'origin/Updates'
parents
63b672c9
3e6ca45f
Changes
4
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Showing
4 changed files
with
96 additions
and
67 deletions
+96
-67
RF24.cpp
RF24.cpp
+65
-63
RF24.h
RF24.h
+10
-2
RF24_config.h
RF24_config.h
+18
-0
RPi/RF24/RF24.cpp
RPi/RF24/RF24.cpp
+3
-2
No files found.
RF24.cpp
View file @
f8791b1d
...
@@ -19,10 +19,10 @@ void RF24::csn(bool mode)
...
@@ -19,10 +19,10 @@ void RF24::csn(bool mode)
// divider of 4 is the minimum we want.
// divider of 4 is the minimum we want.
// CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
// CLK:BUS 8Mhz:2Mhz, 16Mhz:4Mhz, or 20Mhz:5Mhz
#ifdef ARDUINO
#ifdef ARDUINO
#if ( !defined(RF24_TINY) && !defined (__arm__) ) || defined (CORE_TEENSY)
#if ( !defined(RF24_TINY) && !defined (__arm__)
&& !defined (SOFTSPI)
) || defined (CORE_TEENSY)
SPI
.
setBitOrder
(
MSBFIRST
);
_
SPI
.
setBitOrder
(
MSBFIRST
);
SPI
.
setDataMode
(
SPI_MODE0
);
_
SPI
.
setDataMode
(
SPI_MODE0
);
SPI
.
setClockDivider
(
SPI_CLOCK_DIV2
);
_
SPI
.
setClockDivider
(
SPI_CLOCK_DIV2
);
#endif
#endif
#endif
#endif
...
@@ -38,7 +38,7 @@ void RF24::csn(bool mode)
...
@@ -38,7 +38,7 @@ void RF24::csn(bool mode)
}
}
else
{
else
{
PORTB
&=
~
(
1
<<
PINB2
);
// SCK->CSN LOW
PORTB
&=
~
(
1
<<
PINB2
);
// SCK->CSN LOW
delayMicroseconds
(
20
);
// allow csn to settle
delayMicroseconds
(
11
);
// allow csn to settle
}
}
}
}
#else if !defined (__arm__) || defined (CORE_TEENSY)
#else if !defined (__arm__) || defined (CORE_TEENSY)
...
@@ -62,17 +62,17 @@ uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
...
@@ -62,17 +62,17 @@ uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len)
uint8_t
status
;
uint8_t
status
;
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
R_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
status
=
_
SPI
.
transfer
(
csn_pin
,
R_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
while
(
len
--
>
1
){
while
(
len
--
>
1
){
*
buf
++
=
SPI
.
transfer
(
csn_pin
,
0xff
,
SPI_CONTINUE
);
*
buf
++
=
_
SPI
.
transfer
(
csn_pin
,
0xff
,
SPI_CONTINUE
);
}
}
*
buf
++
=
SPI
.
transfer
(
csn_pin
,
0xff
);
*
buf
++
=
_
SPI
.
transfer
(
csn_pin
,
0xff
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
status
=
_
SPI
.
transfer
(
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
while
(
len
--
){
while
(
len
--
){
*
buf
++
=
SPI
.
transfer
(
0xff
);
*
buf
++
=
_
SPI
.
transfer
(
0xff
);
}
}
csn
(
HIGH
);
csn
(
HIGH
);
...
@@ -87,12 +87,12 @@ uint8_t RF24::read_register(uint8_t reg)
...
@@ -87,12 +87,12 @@ uint8_t RF24::read_register(uint8_t reg)
{
{
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
SPI
.
transfer
(
csn_pin
,
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
,
SPI_CONTINUE
);
uint8_t
result
=
SPI
.
transfer
(
csn_pin
,
0xff
);
uint8_t
result
=
_
SPI
.
transfer
(
csn_pin
,
0xff
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
SPI
.
transfer
(
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
_
SPI
.
transfer
(
R_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
uint8_t
result
=
SPI
.
transfer
(
0xff
);
uint8_t
result
=
_
SPI
.
transfer
(
0xff
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
...
@@ -107,17 +107,17 @@ uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
...
@@ -107,17 +107,17 @@ uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len)
uint8_t
status
;
uint8_t
status
;
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
W_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
status
=
_
SPI
.
transfer
(
csn_pin
,
W_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
while
(
--
len
){
while
(
--
len
){
SPI
.
transfer
(
csn_pin
,
*
buf
++
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
*
buf
++
,
SPI_CONTINUE
);
}
}
SPI
.
transfer
(
csn_pin
,
*
buf
++
);
_
SPI
.
transfer
(
csn_pin
,
*
buf
++
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
W_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
status
=
_
SPI
.
transfer
(
W_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
while
(
len
--
)
while
(
len
--
)
SPI
.
transfer
(
*
buf
++
);
_
SPI
.
transfer
(
*
buf
++
);
csn
(
HIGH
);
csn
(
HIGH
);
...
@@ -135,13 +135,13 @@ uint8_t RF24::write_register(uint8_t reg, uint8_t value)
...
@@ -135,13 +135,13 @@ uint8_t RF24::write_register(uint8_t reg, uint8_t value)
IF_SERIAL_DEBUG
(
printf_P
(
PSTR
(
"write_register(%02x,%02x)
\r\n
"
),
reg
,
value
));
IF_SERIAL_DEBUG
(
printf_P
(
PSTR
(
"write_register(%02x,%02x)
\r\n
"
),
reg
,
value
));
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
W_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
status
=
_
SPI
.
transfer
(
csn_pin
,
W_REGISTER
|
(
REGISTER_MASK
&
reg
),
SPI_CONTINUE
);
SPI
.
transfer
(
csn_pin
,
value
);
_
SPI
.
transfer
(
csn_pin
,
value
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
W_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
status
=
_
SPI
.
transfer
(
W_REGISTER
|
(
REGISTER_MASK
&
reg
)
);
SPI
.
transfer
(
value
);
_
SPI
.
transfer
(
value
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
...
@@ -163,32 +163,32 @@ uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t wri
...
@@ -163,32 +163,32 @@ uint8_t RF24::write_payload(const void* buf, uint8_t data_len, const uint8_t wri
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
writeType
,
SPI_CONTINUE
);
status
=
_
SPI
.
transfer
(
csn_pin
,
writeType
,
SPI_CONTINUE
);
if
(
blank_len
){
if
(
blank_len
){
while
(
data_len
--
){
while
(
data_len
--
){
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
}
}
while
(
--
blank_len
){
while
(
--
blank_len
){
SPI
.
transfer
(
csn_pin
,
0
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
0
,
SPI_CONTINUE
);
}
}
SPI
.
transfer
(
csn_pin
,
0
);
_
SPI
.
transfer
(
csn_pin
,
0
);
}
else
{
}
else
{
while
(
--
data_len
){
while
(
--
data_len
){
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
}
}
SPI
.
transfer
(
csn_pin
,
*
current
);
_
SPI
.
transfer
(
csn_pin
,
*
current
);
}
}
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
writeType
);
status
=
_
SPI
.
transfer
(
writeType
);
while
(
data_len
--
)
{
while
(
data_len
--
)
{
SPI
.
transfer
(
*
current
++
);
_
SPI
.
transfer
(
*
current
++
);
}
}
while
(
blank_len
--
)
{
while
(
blank_len
--
)
{
SPI
.
transfer
(
0
);
_
SPI
.
transfer
(
0
);
}
}
csn
(
HIGH
);
csn
(
HIGH
);
...
@@ -212,33 +212,33 @@ uint8_t RF24::read_payload(void* buf, uint8_t data_len)
...
@@ -212,33 +212,33 @@ uint8_t RF24::read_payload(void* buf, uint8_t data_len)
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
R_RX_PAYLOAD
,
SPI_CONTINUE
);
status
=
_
SPI
.
transfer
(
csn_pin
,
R_RX_PAYLOAD
,
SPI_CONTINUE
);
if
(
blank_len
){
if
(
blank_len
){
while
(
data_len
--
){
while
(
data_len
--
){
*
current
++
=
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
*
current
++
=
_
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
}
}
while
(
--
blank_len
){
while
(
--
blank_len
){
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
}
}
SPI
.
transfer
(
csn_pin
,
0xFF
);
_
SPI
.
transfer
(
csn_pin
,
0xFF
);
}
else
{
}
else
{
while
(
--
data_len
){
while
(
--
data_len
){
*
current
++
=
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
*
current
++
=
_
SPI
.
transfer
(
csn_pin
,
0xFF
,
SPI_CONTINUE
);
}
}
*
current
=
SPI
.
transfer
(
csn_pin
,
0xFF
);
*
current
=
_
SPI
.
transfer
(
csn_pin
,
0xFF
);
}
}
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
R_RX_PAYLOAD
);
status
=
_
SPI
.
transfer
(
R_RX_PAYLOAD
);
while
(
data_len
--
)
{
while
(
data_len
--
)
{
*
current
++
=
SPI
.
transfer
(
0xFF
);
*
current
++
=
_
SPI
.
transfer
(
0xFF
);
}
}
while
(
blank_len
--
)
{
while
(
blank_len
--
)
{
SPI
.
transfer
(
0xff
);
_
SPI
.
transfer
(
0xff
);
}
}
csn
(
HIGH
);
csn
(
HIGH
);
...
@@ -267,11 +267,11 @@ uint8_t RF24::spiTrans(uint8_t cmd){
...
@@ -267,11 +267,11 @@ uint8_t RF24::spiTrans(uint8_t cmd){
uint8_t
status
;
uint8_t
status
;
#if defined (__arm__) && !defined ( CORE_TEENSY )
#if defined (__arm__) && !defined ( CORE_TEENSY )
status
=
SPI
.
transfer
(
csn_pin
,
cmd
);
status
=
_
SPI
.
transfer
(
csn_pin
,
cmd
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
status
=
SPI
.
transfer
(
cmd
);
status
=
_
SPI
.
transfer
(
cmd
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
return
status
;
return
status
;
...
@@ -448,15 +448,15 @@ void RF24::begin(void)
...
@@ -448,15 +448,15 @@ void RF24::begin(void)
if
(
ce_pin
!=
csn_pin
)
pinMode
(
ce_pin
,
OUTPUT
);
if
(
ce_pin
!=
csn_pin
)
pinMode
(
ce_pin
,
OUTPUT
);
#if defined(__arm__) && ! defined( CORE_TEENSY )
#if defined(__arm__) && ! defined( CORE_TEENSY )
SPI
.
begin
(
csn_pin
);
// Using the extended SPI features of the DUE
_
SPI
.
begin
(
csn_pin
);
// Using the extended SPI features of the DUE
SPI
.
setClockDivider
(
csn_pin
,
9
);
// Set the bus speed to 8.4mhz on Due
_
SPI
.
setClockDivider
(
csn_pin
,
9
);
// Set the bus speed to 8.4mhz on Due
SPI
.
setBitOrder
(
csn_pin
,
MSBFIRST
);
// Set the bit order and mode specific to this device
_
SPI
.
setBitOrder
(
csn_pin
,
MSBFIRST
);
// Set the bit order and mode specific to this device
SPI
.
setDataMode
(
csn_pin
,
SPI_MODE0
);
_
SPI
.
setDataMode
(
csn_pin
,
SPI_MODE0
);
ce
(
LOW
);
ce
(
LOW
);
//csn(HIGH);
//csn(HIGH);
#else
#else
if
(
ce_pin
!=
csn_pin
)
pinMode
(
csn_pin
,
OUTPUT
);
if
(
ce_pin
!=
csn_pin
)
pinMode
(
csn_pin
,
OUTPUT
);
SPI
.
begin
();
_
SPI
.
begin
();
ce
(
LOW
);
ce
(
LOW
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
...
@@ -836,12 +836,12 @@ uint8_t RF24::getDynamicPayloadSize(void)
...
@@ -836,12 +836,12 @@ uint8_t RF24::getDynamicPayloadSize(void)
uint8_t
result
=
0
;
uint8_t
result
=
0
;
#if defined (__arm__) && ! defined( CORE_TEENSY )
#if defined (__arm__) && ! defined( CORE_TEENSY )
SPI
.
transfer
(
csn_pin
,
R_RX_PL_WID
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
R_RX_PL_WID
,
SPI_CONTINUE
);
result
=
SPI
.
transfer
(
csn_pin
,
0xff
);
result
=
_
SPI
.
transfer
(
csn_pin
,
0xff
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
SPI
.
transfer
(
R_RX_PL_WID
);
_
SPI
.
transfer
(
R_RX_PL_WID
);
result
=
SPI
.
transfer
(
0xff
);
result
=
_
SPI
.
transfer
(
0xff
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
...
@@ -1027,12 +1027,12 @@ void RF24::toggle_features(void)
...
@@ -1027,12 +1027,12 @@ void RF24::toggle_features(void)
{
{
#if defined (__arm__) && ! defined( CORE_TEENSY )
#if defined (__arm__) && ! defined( CORE_TEENSY )
SPI
.
transfer
(
csn_pin
,
ACTIVATE
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
ACTIVATE
,
SPI_CONTINUE
);
SPI
.
transfer
(
csn_pin
,
0x73
);
_
SPI
.
transfer
(
csn_pin
,
0x73
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
SPI
.
transfer
(
ACTIVATE
);
_
SPI
.
transfer
(
ACTIVATE
);
SPI
.
transfer
(
0x73
);
_
SPI
.
transfer
(
0x73
);
csn
(
HIGH
);
csn
(
HIGH
);
#endif
#endif
}
}
...
@@ -1102,18 +1102,18 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
...
@@ -1102,18 +1102,18 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
uint8_t
data_len
=
min
(
len
,
32
);
uint8_t
data_len
=
min
(
len
,
32
);
#if defined (__arm__) && ! defined( CORE_TEENSY )
#if defined (__arm__) && ! defined( CORE_TEENSY )
SPI
.
transfer
(
csn_pin
,
W_ACK_PAYLOAD
|
(
pipe
&
B111
),
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
W_ACK_PAYLOAD
|
(
pipe
&
B111
),
SPI_CONTINUE
);
while
(
data_len
--
>
1
){
while
(
data_len
--
>
1
){
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
_
SPI
.
transfer
(
csn_pin
,
*
current
++
,
SPI_CONTINUE
);
}
}
SPI
.
transfer
(
csn_pin
,
*
current
++
);
_
SPI
.
transfer
(
csn_pin
,
*
current
++
);
#else
#else
csn
(
LOW
);
csn
(
LOW
);
SPI
.
transfer
(
W_ACK_PAYLOAD
|
(
pipe
&
B111
)
);
_
SPI
.
transfer
(
W_ACK_PAYLOAD
|
(
pipe
&
B111
)
);
while
(
data_len
--
)
while
(
data_len
--
)
SPI
.
transfer
(
*
current
++
);
_
SPI
.
transfer
(
*
current
++
);
csn
(
HIGH
);
csn
(
HIGH
);
...
@@ -1292,9 +1292,11 @@ void RF24::setCRCLength(rf24_crclength_e length)
...
@@ -1292,9 +1292,11 @@ void RF24::setCRCLength(rf24_crclength_e length)
rf24_crclength_e
RF24
::
getCRCLength
(
void
)
rf24_crclength_e
RF24
::
getCRCLength
(
void
)
{
{
rf24_crclength_e
result
=
RF24_CRC_DISABLED
;
rf24_crclength_e
result
=
RF24_CRC_DISABLED
;
uint8_t
config
=
read_register
(
CONFIG
)
&
(
_BV
(
CRCO
)
|
_BV
(
EN_CRC
))
;
uint8_t
config
=
read_register
(
CONFIG
)
&
(
_BV
(
CRCO
)
|
_BV
(
EN_CRC
))
;
uint8_t
AA
=
read_register
(
EN_AA
);
if
(
config
&
_BV
(
EN_CRC
)
)
if
(
config
&
_BV
(
EN_CRC
)
||
AA
)
{
{
if
(
config
&
_BV
(
CRCO
)
)
if
(
config
&
_BV
(
CRCO
)
)
result
=
RF24_CRC_16
;
result
=
RF24_CRC_16
;
...
...
RF24.h
View file @
f8791b1d
...
@@ -16,7 +16,9 @@
...
@@ -16,7 +16,9 @@
#define __RF24_H__
#define __RF24_H__
#include <RF24_config.h>
#include <RF24_config.h>
#if defined SOFTSPI
#include <DigitalIO.h>
#endif
/**
/**
* Power Amplifier level.
* Power Amplifier level.
*
*
...
@@ -45,6 +47,12 @@ typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e
...
@@ -45,6 +47,12 @@ typedef enum { RF24_CRC_DISABLED = 0, RF24_CRC_8, RF24_CRC_16 } rf24_crclength_e
class
RF24
class
RF24
{
{
private:
private:
#ifdef SOFTSPI
SoftSPI
<
SOFT_SPI_MISO_PIN
,
SOFT_SPI_MOSI_PIN
,
SOFT_SPI_SCK_PIN
,
SPI_MODE
>
spi
;
#elif defined (SPI_UART)
SPIUARTClass
uspi
;
#endif
uint8_t
ce_pin
;
/**< "Chip Enable" pin, activates the RX or TX role */
uint8_t
ce_pin
;
/**< "Chip Enable" pin, activates the RX or TX role */
uint8_t
csn_pin
;
/**< SPI Chip select */
uint8_t
csn_pin
;
/**< SPI Chip select */
bool
p_variant
;
/* False for RF24L01 and true for RF24L01P */
bool
p_variant
;
/* False for RF24L01 and true for RF24L01P */
...
@@ -223,7 +231,7 @@ public:
...
@@ -223,7 +231,7 @@ public:
* @@return True if all three 32-byte radio buffers are full
* @@return True if all three 32-byte radio buffers are full
*/
*/
bool
rxFifoFull
();
bool
rxFifoFull
();
/**
/**
* Enter low-power mode
* Enter low-power mode
*
*
...
...
RF24_config.h
View file @
f8791b1d
...
@@ -24,14 +24,32 @@
...
@@ -24,14 +24,32 @@
//#define FAILURE_HANDLING
//#define FAILURE_HANDLING
//#define SERIAL_DEBUG
//#define SERIAL_DEBUG
//#define MINIMAL
//#define MINIMAL
//#define SPI_UART
//#define SOFTSPI
/**********************/
/**********************/
// Define _BV for non-Arduino platforms and for Arduino DUE
// Define _BV for non-Arduino platforms and for Arduino DUE
#if defined (ARDUINO) && !defined (__arm__)
#if defined (ARDUINO) && !defined (__arm__)
#if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
#if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) || defined(__AVR_ATtiny24__) || defined(__AVR_ATtiny44__) || defined(__AVR_ATtiny84__)
#define RF24_TINY
#define RF24_TINY
#define _SPI SPI
#else
#else
#if defined SPI_UART
#include <SPI_UART.h>
#define _SPI uspi
#elif defined SOFTSPI
// change these pins to your liking
//
const
uint8_t
SOFT_SPI_MISO_PIN
=
16
;
const
uint8_t
SOFT_SPI_MOSI_PIN
=
15
;
const
uint8_t
SOFT_SPI_SCK_PIN
=
14
;
const
uint8_t
SPI_MODE
=
0
;
#define _SPI spi
#else
#include <SPI.h>
#include <SPI.h>
#define _SPI SPI
#endif
#endif
#endif
#else
#else
...
...
RPi/RF24/RF24.cpp
View file @
f8791b1d
...
@@ -1233,8 +1233,9 @@ rf24_crclength_e RF24::getCRCLength(void)
...
@@ -1233,8 +1233,9 @@ rf24_crclength_e RF24::getCRCLength(void)
{
{
rf24_crclength_e
result
=
RF24_CRC_DISABLED
;
rf24_crclength_e
result
=
RF24_CRC_DISABLED
;
uint8_t
config
=
read_register
(
CONFIG
)
&
(
_BV
(
CRCO
)
|
_BV
(
EN_CRC
))
;
uint8_t
config
=
read_register
(
CONFIG
)
&
(
_BV
(
CRCO
)
|
_BV
(
EN_CRC
))
;
uint8_t
AA
=
read_register
(
EN_AA
);
if
(
config
&
_BV
(
EN_CRC
)
)
if
(
config
&
_BV
(
EN_CRC
)
||
AA
)
{
{
if
(
config
&
_BV
(
CRCO
)
)
if
(
config
&
_BV
(
CRCO
)
)
result
=
RF24_CRC_16
;
result
=
RF24_CRC_16
;
...
...
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