Commit aaa09e18 authored by TMRh20's avatar TMRh20

Per #242 change binary to hex

- Change binary to hex
- Assign csDelay value in constructor
parent b9a4fc67
...@@ -357,7 +357,7 @@ void RF24::print_status(uint8_t status) ...@@ -357,7 +357,7 @@ void RF24::print_status(uint8_t status)
(status & _BV(RX_DR))?1:0, (status & _BV(RX_DR))?1:0,
(status & _BV(TX_DS))?1:0, (status & _BV(TX_DS))?1:0,
(status & _BV(MAX_RT))?1:0, (status & _BV(MAX_RT))?1:0,
((status >> RX_P_NO) & 0b111), ((status >> RX_P_NO) & 0x07),
(status & _BV(TX_FULL))?1:0 (status & _BV(TX_FULL))?1:0
); );
} }
...@@ -368,8 +368,8 @@ void RF24::print_observe_tx(uint8_t value) ...@@ -368,8 +368,8 @@ void RF24::print_observe_tx(uint8_t value)
{ {
printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), printf_P(PSTR("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"),
value, value,
(value >> PLOS_CNT) & 0b1111, (value >> PLOS_CNT) & 0x0F,
(value >> ARC_CNT) & 0b1111 (value >> ARC_CNT) & 0x0F
); );
} }
...@@ -417,7 +417,7 @@ void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) ...@@ -417,7 +417,7 @@ void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
RF24::RF24(uint8_t _cepin, uint8_t _cspin): RF24::RF24(uint8_t _cepin, uint8_t _cspin):
ce_pin(_cepin), csn_pin(_cspin), p_variant(false), ce_pin(_cepin), csn_pin(_cspin), p_variant(false),
payload_size(32), dynamic_payloads_enabled(false), addr_width(5)//,pipe0_reading_address(0) payload_size(32), dynamic_payloads_enabled(false), addr_width(5),csDelay(5)//,pipe0_reading_address(0)
{ {
pipe0_reading_address[0]=0; pipe0_reading_address[0]=0;
} }
...@@ -426,7 +426,7 @@ RF24::RF24(uint8_t _cepin, uint8_t _cspin): ...@@ -426,7 +426,7 @@ RF24::RF24(uint8_t _cepin, uint8_t _cspin):
#if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor #if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor
RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed): RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed):
ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5)//,pipe0_reading_address(0) ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5),csDelay(5)//,pipe0_reading_address(0)
{ {
pipe0_reading_address[0]=0; pipe0_reading_address[0]=0;
} }
...@@ -634,7 +634,7 @@ bool RF24::begin(void) ...@@ -634,7 +634,7 @@ bool RF24::begin(void)
delay( 5 ) ; delay( 5 ) ;
// Reset NRF_CONFIG and enable 16-bit CRC. // Reset NRF_CONFIG and enable 16-bit CRC.
write_register( NRF_CONFIG, 0b00001100 ) ; write_register( NRF_CONFIG, 0x0C ) ;
// Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier
// WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet
...@@ -1071,7 +1071,7 @@ bool RF24::available(uint8_t* pipe_num) ...@@ -1071,7 +1071,7 @@ bool RF24::available(uint8_t* pipe_num)
// If the caller wants the pipe number, include that // If the caller wants the pipe number, include that
if ( pipe_num ){ if ( pipe_num ){
uint8_t status = get_status(); uint8_t status = get_status();
*pipe_num = ( status >> RX_P_NO ) & 0b111; *pipe_num = ( status >> RX_P_NO ) & 0x07;
} }
return 1; return 1;
} }
...@@ -1181,7 +1181,10 @@ void RF24::setAddressWidth(uint8_t a_width){ ...@@ -1181,7 +1181,10 @@ void RF24::setAddressWidth(uint8_t a_width){
if(a_width -= 2){ if(a_width -= 2){
write_register(SETUP_AW,a_width%4); write_register(SETUP_AW,a_width%4);
addr_width = (a_width%4) + 2; addr_width = (a_width%4) + 2;
} }else{
write_register(SETUP_AW,0);
addr_width = 2;
}
} }
...@@ -1298,7 +1301,7 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) ...@@ -1298,7 +1301,7 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
beginTransaction(); beginTransaction();
uint8_t * ptx = spi_txbuff; uint8_t * ptx = spi_txbuff;
uint8_t size = data_len + 1 ; // Add register value to transmit buffer uint8_t size = data_len + 1 ; // Add register value to transmit buffer
*ptx++ = W_ACK_PAYLOAD | ( pipe & 0b111 ); *ptx++ = W_ACK_PAYLOAD | ( pipe & 0x07 );
while ( data_len-- ){ while ( data_len-- ){
*ptx++ = *current++; *ptx++ = *current++;
} }
...@@ -1307,7 +1310,7 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) ...@@ -1307,7 +1310,7 @@ void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len)
endTransaction(); endTransaction();
#else #else
beginTransaction(); beginTransaction();
_SPI.transfer(W_ACK_PAYLOAD | ( pipe & 0b111 ) ); _SPI.transfer(W_ACK_PAYLOAD | ( pipe & 0x07 ) );
while ( data_len-- ) while ( data_len-- )
_SPI.transfer(*current++); _SPI.transfer(*current++);
...@@ -1336,7 +1339,7 @@ bool RF24::isPVariant(void) ...@@ -1336,7 +1339,7 @@ bool RF24::isPVariant(void)
void RF24::setAutoAck(bool enable) void RF24::setAutoAck(bool enable)
{ {
if ( enable ) if ( enable )
write_register(EN_AA, 0b111111); write_register(EN_AA, 0x3F);
else else
write_register(EN_AA, 0); write_register(EN_AA, 0);
} }
...@@ -1379,7 +1382,7 @@ bool RF24::testRPD(void) ...@@ -1379,7 +1382,7 @@ bool RF24::testRPD(void)
void RF24::setPALevel(uint8_t level) void RF24::setPALevel(uint8_t level)
{ {
uint8_t setup = read_register(RF_SETUP) & 0b11111000; uint8_t setup = read_register(RF_SETUP) & 0xF8;
if(level > 3){ // If invalid level, go to max PA if(level > 3){ // If invalid level, go to max PA
level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit
......
...@@ -928,7 +928,7 @@ s * ...@@ -928,7 +928,7 @@ s *
* If using interrupts or timed requests, this can be set to 0 Default:5 * If using interrupts or timed requests, this can be set to 0 Default:5
*/ */
uint32_t csDelay=5; uint32_t csDelay;
/**@}*/ /**@}*/
/** /**
......
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