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picsimlab
Commit 82f69827 authored by lcgamboa's avatar lcgamboa
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new: Add support to PWM outputs for ESP32C3 and STM32 boards

parent 0e883416
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Showing with 1253 additions and 284 deletions
src/boards/board_Blue_Pill.cc
View file @ 82f69827
......@@ -43,6 +43,84 @@ enum {
O_RST // Reset button
};
// copied from qemu, must be the same
enum {
STM32_PERIPH_UNDEFINED = -1,
STM32_RCC_PERIPH = 0,
STM32_GPIOA,
STM32_GPIOB,
STM32_GPIOC,
STM32_GPIOD,
STM32_GPIOE,
STM32_GPIOF,
STM32_GPIOG,
STM32_GPIOH,
STM32_GPIOI,
STM32_GPIOJ,
STM32_GPIOK,
STM32_SYSCFG,
STM32_AFIO_PERIPH,
STM32_UART1,
STM32_UART2,
STM32_UART3,
STM32_UART4,
STM32_UART5,
STM32_UART6,
STM32_UART7,
STM32_UART8,
STM32_ADC1,
STM32_ADC2,
STM32_ADC3,
STM32_DAC,
STM32_TIM1,
STM32_TIM2,
STM32_TIM3,
STM32_TIM4,
STM32_TIM5,
STM32_TIM6,
STM32_TIM7,
STM32_TIM8,
STM32_TIM9,
STM32_TIM10,
STM32_TIM11,
STM32_TIM12,
STM32_TIM13,
STM32_TIM14,
STM32_BKP,
STM32_PWR,
STM32_I2C1,
STM32_I2C2,
STM32_I2C3,
STM32_I2S2,
STM32_I2S3,
STM32_WWDG,
STM32_IWDG,
STM32_CAN1,
STM32_CAN2,
STM32_CAN,
STM32_USB,
STM32_SPI1,
STM32_SPI2,
STM32_SPI3,
STM32_EXTI_PERIPH,
STM32_SDIO,
STM32_FSMC,
STM32_RTC,
STM32_COMP,
STM_LCD,
STM32_CRC,
STM32_DMA1,
STM32_DMA2,
STM32_DCMI_PERIPH,
STM32_CRYP_PERIPH,
STM32_HASH_PERIPH,
STM32_RNG_PERIPH,
STM32_FLASH,
STM32_FLASH_REGS,
STM32_PERIPH_COUNT,
};
#define A 0x1000
#define B 0x2000
#define C 0x3000
......@@ -100,6 +178,17 @@ static const short int pinmap[49] = {
-1 // 48 VDD
};
static unsigned char iopin(const unsigned short port, const unsigned int num) {
unsigned char pin = 0;
unsigned short value = port | num;
for (int i = 0; i < 49; i++) {
if (pinmap[i] == value) {
pin = i;
}
}
return pin;
}
const short int* cboard_Blue_Pill::GetPinMap(void) {
return pinmap;
}
......@@ -168,6 +257,8 @@ cboard_Blue_Pill::cboard_Blue_Pill(void) {
master_uart[2].tx_pin = 0;
master_uart[2].rx_pin = 0;
bitbang_pwm_init(&pwm_out, this, 20);
if (PICSimLab.GetWindow()) {
// label1
label1 = new CLabel();
......@@ -207,6 +298,7 @@ cboard_Blue_Pill::~cboard_Blue_Pill(void) {
PICSimLab.GetWindow()->DestroyChild(label1);
PICSimLab.GetWindow()->DestroyChild(combo1);
}
bitbang_pwm_end(&pwm_out);
}
// Reset board status
......@@ -687,113 +779,396 @@ void cboard_Blue_Pill::MSetAPin(int pin, float value) {
}
void cboard_Blue_Pill::PinsExtraConfig(int cfg) {
if ((cfg & 0x8008) == 0x8008) { // Alternate function
int pin = (cfg & 0x7FF0) >> 4;
if ((cfg & 0xF00008) == 0x800008) { // Alternate function
int pin = (cfg & 0x0FF0) >> 4;
int port = cfg & 0x0003;
uint32_t* uart_afio;
uint32_t* afio;
// int cfg_ = (cfg & 0x000C) >> 2;
// printf("Extra CFG port(%i) pin[%02i]=0x%02X \n", port, pin, cfg_);
// printf("Extra CFG Alternate function port(%c) pin[%02i]=0x%02X \n", port + 'A', pin, cfg_);
switch (port) {
case 0: // GPIOA
switch (pin) {
case 2: // uart2
uart_afio = qemu_picsimlab_get_internals(0x1000 | 15);
if (!(*uart_afio)) {
case 0:
// tim2 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 0] = iopin(A, 0);
}
break;
case 1:
// tim2 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 1] = iopin(A, 1);
}
break;
case 2:
// uart2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART2);
if (!(*afio)) {
master_uart[1].tx_pin = iopin(A, 2);
master_uart[1].rx_pin = iopin(A, 3);
master_uart[1].ctrl_on = 1;
break;
}
// tim2 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 2] = iopin(A, 2);
}
break;
case 3:
// uart2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART2);
if (!(*afio)) {
master_uart[1].tx_pin = iopin(A, 2);
master_uart[1].rx_pin = iopin(A, 3);
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = 12; // pa2
master_uart[1].rx_pin = 13; // pa3
break;
}
// tim2 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 3] = iopin(A, 3);
}
break;
case 4:
break;
case 5:
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
}
break;
case 6:
case 7: // spi1
uart_afio = qemu_picsimlab_get_internals(0x1000 | 53);
if (!(*uart_afio)) {
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = 15; // pa5
master_spi[0].copi_pin = 17; // pa7
master_spi[0].cipo_pin = 16; // pa6
break;
}
// tim3 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 0] = iopin(A, 6);
}
break;
case 9: // uart1
uart_afio = qemu_picsimlab_get_internals(0x1000 | 14);
if (!(*uart_afio)) {
case 7:
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
break;
}
// tim1_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 7);
break;
}
// tim3 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 1] = iopin(A, 7);
}
break;
case 8:
// tim1 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 8);
}
break;
case 9:
// uart1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if (!(*afio)) {
master_uart[0].tx_pin = iopin(A, 9);
master_uart[0].rx_pin = iopin(A, 10);
master_uart[0].ctrl_on = 1;
break;
}
// tim1 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 1] = iopin(A, 9);
}
break;
case 10:
// uart1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if (!(*afio)) {
master_uart[0].tx_pin = iopin(A, 9);
master_uart[0].rx_pin = iopin(A, 10);
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = 30; // pa9
master_uart[0].rx_pin = 31; // pa10
break;
}
// tim1 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 2] = iopin(A, 10);
}
break;
case 11:
// tim1 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 3] = iopin(A, 11);
}
break;
case 12:
break;
case 13:
break;
case 14:
break;
case 15:
break;
}
break;
case 1: // GPIOB
switch (pin) {
case 0:
// tim1_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 1] = iopin(B, 0);
break;
}
// tim3_ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 2] = iopin(B, 0);
}
break;
case 1:
// tim1_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 2] = iopin(B, 1);
break;
}
// tim3_ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 3] = iopin(B, 1);
}
break;
case 2:
break;
case 3:
// tim2_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 1] = iopin(B, 3);
break;
}
case 4:
case 5: // spi1 (alt)
uart_afio = qemu_picsimlab_get_internals(0x1000 | 53);
if (!(*uart_afio)) {
// tim3_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 0] = iopin(B, 4);
break;
}
case 5:
// spi1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(B, 3);
master_spi[0].copi_pin = iopin(B, 5);
master_spi[0].cipo_pin = iopin(B, 4);
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = 39; // pb3
master_spi[0].copi_pin = 41; // pb5
master_spi[0].cipo_pin = 40; // pb4
break;
}
// tim3_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 1] = iopin(B, 5);
break;
}
break;
case 6: // uart1 (alt) and i2c
uart_afio = qemu_picsimlab_get_internals(0x1000 | 14);
if ((*uart_afio)) {
case 6:
// uart1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if ((*afio)) {
master_uart[0].tx_pin = iopin(B, 6);
master_uart[0].rx_pin = iopin(B, 7);
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = 42; // pb6
master_uart[0].rx_pin = 43; // pb7
break;
}
// break;
case 7: // i2c0
uart_afio = qemu_picsimlab_get_internals(0x1000 | 42);
if (!(*uart_afio)) {
// i2c
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (!(*afio)) {
master_i2c[0].scl_pin = iopin(B, 6);
master_i2c[0].sda_pin = iopin(B, 7);
master_i2c[0].ctrl_on = 1;
break;
}
// tim4 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 0] = iopin(B, 6);
}
break;
case 7:
// uart1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if ((*afio)) {
master_uart[0].tx_pin = iopin(B, 6);
master_uart[0].rx_pin = iopin(B, 7);
master_uart[0].ctrl_on = 1;
break;
}
// i2c0
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (!(*afio)) {
master_i2c[0].scl_pin = iopin(B, 6);
master_i2c[0].sda_pin = iopin(B, 7);
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = 42; // pb6
master_i2c[0].sda_pin = 43; // pb7
break;
}
// tim4 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 1] = iopin(B, 7);
}
break;
case 8:
case 9: // i2c0 (alt)
uart_afio = qemu_picsimlab_get_internals(0x1000 | 42);
if ((*uart_afio)) {
// i2c0 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if ((*afio)) {
master_i2c[0].scl_pin = iopin(B, 8);
master_i2c[0].sda_pin = iopin(B, 9);
master_i2c[0].ctrl_on = 1;
break;
}
// tim4 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 2] = iopin(B, 8);
}
case 9:
// i2c0 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if ((*afio)) {
master_i2c[0].scl_pin = iopin(B, 8);
master_i2c[0].sda_pin = iopin(B, 9);
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = 45; // pb8
master_i2c[0].sda_pin = 46; // pb9
break;
}
// tim4 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 3] = iopin(B, 9);
}
break;
case 10:
// tim2_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 2] = iopin(B, 10);
break;
case 10: // uart3
}
/*
uart_afio = qemu_picsimlab_get_internals(0x1000 | 16);
// uart3
uart_afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART3);
if (!(*uart_afio)) {
master_uart[2].tx_pin = iopin(B, 10);
master_uart[2].rx_pin = iopin(B, 11);
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = 21; // pb10
master_uart[2].rx_pin = 22; // pb11
break
}
*/
case 11: // i2c1
// i2c1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (*afio == 0) {
master_i2c[1].scl_pin = iopin(B, 10);
master_i2c[1].sda_pin = iopin(B, 11);
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = 21; // pb10
master_i2c[1].sda_pin = 22; // pb11
break;
}
break;
case 11:
// tim2_ch4n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 3] = iopin(B, 10);
break;
}
/*
// uart3
uart_afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART3);
if (!(*uart_afio)) {
master_uart[2].tx_pin = iopin(B, 10);
master_uart[2].rx_pin = iopin(B, 11);
master_uart[2].ctrl_on = 1;
break;
}
*/
// i2c1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (*afio == 0) {
master_i2c[1].scl_pin = iopin(B, 10);
master_i2c[1].sda_pin = iopin(B, 11);
master_i2c[1].ctrl_on = 1;
break;
}
break;
case 12:
break;
case 13:
case 14:
case 15: // spi2
case 15:
// spi2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI2);
if (*afio == 0) {
master_spi[1].sck_pin = iopin(B, 13);
master_spi[1].copi_pin = iopin(B, 15);
master_spi[1].cipo_pin = iopin(B, 14);
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = 26; // pb13
master_spi[1].copi_pin = 28; // pb15
master_spi[1].cipo_pin = 27; // pb14
}
break;
}
break;
/*
case 2: // GPIOC
switch (pin) {
case 13:
break;
case 14:
break;
case 15:
break;
}
break;
case 3: // GPIOD
switch (pin) {
case 0:
break;
case 1:
break;
}
break;
*/
}
} else if ((cfg & 0xF00000) == 0xC00000) { // timer ccmr1 function
int duty = (cfg & 0xFFFF0) >> 4;
int chn = (cfg & 0x000C) >> 2;
int timer = cfg & 0x0003;
// printf("TIM %i chn %i dut set to %i\n", timer + 1, chn + 1, duty);
bitbang_pwm_set_duty(&pwm_out, (timer << 2) + chn, duty);
}
}
......
src/boards/board_C3_DevKitC.cc
View file @ 82f69827
......@@ -248,7 +248,7 @@ cboard_C3_DevKitC::cboard_C3_DevKitC(void) {
master_uart[2].tx_pin = 0;
master_uart[2].rx_pin = 0;
bitbang_pwm_init(&ledc, this, 6);
bitbang_pwm_init(&pwm_out, this, 6);
if (PICSimLab.GetWindow()) {
// label1
......@@ -316,7 +316,7 @@ cboard_C3_DevKitC::~cboard_C3_DevKitC(void) {
wconfig->SetCanDestroy(true);
wconfig->WDestroy();
}
bitbang_pwm_end(&ledc);
bitbang_pwm_end(&pwm_out);
}
// Reset board status
......@@ -805,45 +805,45 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
switch (function) {
/*
case 9: // HSPIQ
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
*/
case 6: // U0RXD
master_uart[0].ctrl_on = 1;
master_uart[0].rx_pin = io2pin(gpio);
master_uart[0].ctrl_on = 1;
break;
case 9: // U1RXD
master_uart[1].ctrl_on = 1;
master_uart[1].rx_pin = io2pin(gpio);
master_uart[1].ctrl_on = 1;
break;
/*
case 29: // I2CEXT0_SCL
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 30: // I2CEXT0_SDA
master_i2c[0].ctrl_on = 1;
master_i2c[0].sda_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 64: // VSPIQ
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 95: // I2CEXT1_SCL
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 96: // I2CEXT1_SDA
master_i2c[1].ctrl_on = 1;
master_i2c[1].sda_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 198: // U2RXD
master_uart[2].ctrl_on = 1;
master_uart[2].rx_pin = io2pin(gpio);
master_uart[2].ctrl_on = 1;
break;
*/
}
......@@ -860,86 +860,86 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
switch (function) {
/*
case 8: // HSPICLK
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 9: // HSPIQ
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 10: // HSPID
master_spi[0].ctrl_on = 1;
master_spi[0].copi_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 11: // HSPICS0
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[0] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
*/
case 6: // U0TXD
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = io2pin(gpio);
master_uart[0].ctrl_on = 1;
break;
case 9: // U1TXD
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = io2pin(gpio);
master_uart[1].ctrl_on = 1;
break;
/*
case 29: // I2CEXT0_SCL
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 30: // I2CEXT0_SDA
master_i2c[0].ctrl_on = 1;
master_i2c[0].sda_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 61: // HSPICS1
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[1] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 62: // HSPICS2
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[2] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 63: // VSPICLK
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 64: // VSPIQ
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 65: // VSPID
master_spi[1].ctrl_on = 1;
master_spi[1].copi_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 68: // VSPICS0
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[0] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 69: // VSPICS1
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[1] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 70: // VSPICS2
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[2] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 95: // I2CEXT1_SCL
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 96: // I2CEXT1_SDA
master_i2c[1].ctrl_on = 1;
master_i2c[1].sda_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 198: // U2RTXD
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = io2pin(gpio);
master_uart[2].ctrl_on = 1;
break;
*/
case 45: // ledc_ls_sig_out0
......@@ -949,7 +949,7 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
case 49: // ledc_ls_sig_out4
case 50: // ledc_ls_sig_out5
// printf("LEDC channel %i in GPIO %i\n", function - 45, gpio);
ledc.pins[function - 45] = io2pin(gpio);
pwm_out.pins[function - 45] = io2pin(gpio);
break;
case 51: // rmt_sig_out0
case 52: // rmt_sig_out1
......@@ -969,12 +969,12 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
case 0:
switch (gpio) {
case 21:
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = IO21;
master_uart[0].ctrl_on = 1;
break;
case 20:
master_uart[0].ctrl_on = 1;
master_uart[0].rx_pin = IO20;
master_uart[0].ctrl_on = 1;
break;
}
break;
......@@ -982,36 +982,36 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
/*
switch (gpio) {
case 12:
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = IO12;
master_spi[0].ctrl_on = 1;
break;
case 13:
master_spi[0].ctrl_on = 1;
master_spi[0].copi_pin = IO13;
master_spi[0].ctrl_on = 1;
break;
case 14:
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = IO14;
master_spi[0].ctrl_on = 1;
break;
case 15:
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[0] = IO15;
master_spi[0].ctrl_on = 1;
break;
case 18:
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = IO18;
master_spi[1].ctrl_on = 1;
break;
case 19:
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = IO19;
master_spi[1].ctrl_on = 1;
break;
case 23:
master_spi[1].ctrl_on = 1;
master_spi[1].copi_pin = IO23;
master_spi[1].ctrl_on = 1;
break;
case 5:
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[0] = IO5;
master_spi[1].ctrl_on = 1;
break;
}*/
break;
......@@ -1023,20 +1023,20 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
/*
switch (gpio) {
case 9:
master_uart[1].ctrl_on = 1;
master_uart[1].rx_pin = IO9;
master_uart[1].ctrl_on = 1;
break;
case 10:
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = IO10;
master_uart[1].ctrl_on = 1;
break;
case 16:
master_uart[2].ctrl_on = 1;
master_uart[2].rx_pin = IO16;
master_uart[2].ctrl_on = 1;
break;
case 17:
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = IO17;
master_uart[2].ctrl_on = 1;
break;
}
break;
......@@ -1047,7 +1047,7 @@ void cboard_C3_DevKitC::PinsExtraConfig(int cfg) {
} break;
case QEMU_EXTRA_PIN_LEDC_CFG:
bitbang_pwm_set_duty(&ledc, (cfg & 0x0F00) >> 8, cfg & 0xFF);
bitbang_pwm_set_duty(&pwm_out, (cfg & 0x0F00) >> 8, cfg & 0xFF);
break;
}
}
......@@ -1158,60 +1158,29 @@ int cboard_C3_DevKitC::MGetPinCount(void) {
void cboard_C3_DevKitC::MSetAPin(int pin, float value) {
if (!pin)
return;
/*
if ((pins[pin - 1].avalue != value)) {
unsigned char channel = 0xFF;
pins[pin - 1].avalue = value;
switch (pin) {
case IO36:
case IO0:
channel = 0;
break;
case IO39:
channel = 3;
break;
case IO32:
channel = 4;
break;
case IO33:
channel = 5;
break;
case IO34:
channel = 6;
break;
case IO35:
channel = 7;
break;
case IO4:
channel = 0x8 + 0;
break;
case IO0:
channel = 0x8 + 1;
case IO1:
channel = 1;
break;
case IO2:
channel = 0x8 + 2;
break;
case IO15:
channel = 0x8 + 3;
break;
case IO13:
channel = 0x8 + 4;
break;
case IO12:
channel = 0x8 + 5;
channel = 2;
break;
case IO14:
channel = 0x8 + 6;
break;
case IO27:
channel = 0x8 + 7;
case IO3:
channel = 3;
break;
case IO25:
channel = 0x8 + 8;
case IO4:
channel = 4;
break;
case IO26:
channel = 0x8 + 9;
case IO5:
channel = 0x8 + 0;
break;
}
......@@ -1232,7 +1201,6 @@ void cboard_C3_DevKitC::MSetAPin(int pin, float value) {
}
}
}
*/
}
// Register the board in PICSimLab
......
src/boards/board_DevKitC.cc
View file @ 82f69827
......@@ -309,7 +309,7 @@ cboard_DevKitC::cboard_DevKitC(void) {
master_uart[2].tx_pin = 0;
master_uart[2].rx_pin = 0;
bitbang_pwm_init(&ledc, this, 16);
bitbang_pwm_init(&pwm_out, this, 16);
if (PICSimLab.GetWindow()) {
// label1
......@@ -377,7 +377,7 @@ cboard_DevKitC::~cboard_DevKitC(void) {
wconfig->SetCanDestroy(true);
wconfig->WDestroy();
}
bitbang_pwm_end(&ledc);
bitbang_pwm_end(&pwm_out);
}
// Reset board status
......@@ -861,45 +861,45 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
switch (function) {
case 9: // HSPIQ
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 14: // U0RXD
master_uart[0].ctrl_on = 1;
master_uart[0].rx_pin = io2pin(gpio);
master_uart[0].ctrl_on = 1;
break;
case 17: // U1RXD
master_uart[1].ctrl_on = 1;
master_uart[1].rx_pin = io2pin(gpio);
master_uart[1].ctrl_on = 1;
break;
case 29: // I2CEXT0_SCL
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 30: // I2CEXT0_SDA
master_i2c[0].ctrl_on = 1;
master_i2c[0].sda_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 64: // VSPIQ
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 95: // I2CEXT1_SCL
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 96: // I2CEXT1_SDA
master_i2c[1].ctrl_on = 1;
master_i2c[1].sda_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 198: // U2RXD
master_uart[2].ctrl_on = 1;
master_uart[2].rx_pin = io2pin(gpio);
master_uart[2].ctrl_on = 1;
break;
}
......@@ -913,72 +913,72 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
switch (function) {
case 8: // HSPICLK
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 9: // HSPIQ
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 10: // HSPID
master_spi[0].ctrl_on = 1;
master_spi[0].copi_pin = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 11: // HSPICS0
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[0] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 14: // U0TXD
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = io2pin(gpio);
master_uart[0].ctrl_on = 1;
break;
case 17: // U1TXD
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = io2pin(gpio);
master_uart[1].ctrl_on = 1;
break;
case 29: // I2CEXT0_SCL
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 30: // I2CEXT0_SDA
master_i2c[0].ctrl_on = 1;
master_i2c[0].sda_pin = io2pin(gpio);
master_i2c[0].ctrl_on = 1;
break;
case 61: // HSPICS1
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[1] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 62: // HSPICS2
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[2] = io2pin(gpio);
master_spi[0].ctrl_on = 1;
break;
case 63: // VSPICLK
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 64: // VSPIQ
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 65: // VSPID
master_spi[1].ctrl_on = 1;
master_spi[1].copi_pin = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 68: // VSPICS0
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[0] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 69: // VSPICS1
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[1] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 70: // VSPICS2
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[2] = io2pin(gpio);
master_spi[1].ctrl_on = 1;
break;
case 71: // ledc_hs_sig_out0
case 72: // ledc_hs_sig_out1
......@@ -997,7 +997,7 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
case 85: // ledc_ls_sig_out6
case 86: // ledc_ls_sig_out7
// printf("LEDC channel %i in GPIO %i\n", function - 71, gpio);
ledc.pins[function - 71] = io2pin(gpio);
pwm_out.pins[function - 71] = io2pin(gpio);
break;
case 87: // rmt_sig_out0
case 88: // rmt_sig_out1
......@@ -1010,17 +1010,17 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
// printf("RMT channel %i in GPIO %i\n", function - 71, gpio);
break;
case 95: // I2CEXT1_SCL
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 96: // I2CEXT1_SDA
master_i2c[1].ctrl_on = 1;
master_i2c[1].sda_pin = io2pin(gpio);
master_i2c[1].ctrl_on = 1;
break;
case 198: // U2RTXD
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = io2pin(gpio);
master_uart[2].ctrl_on = 1;
break;
}
......@@ -1036,48 +1036,48 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
case 0:
switch (gpio) {
case 1:
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = IO1;
master_uart[0].ctrl_on = 1;
break;
case 3:
master_uart[0].ctrl_on = 1;
master_uart[0].rx_pin = IO3;
master_uart[0].ctrl_on = 1;
break;
}
break;
case 1:
switch (gpio) {
case 12:
master_spi[0].ctrl_on = 1;
master_spi[0].cipo_pin = IO12;
master_spi[0].ctrl_on = 1;
break;
case 13:
master_spi[0].ctrl_on = 1;
master_spi[0].copi_pin = IO13;
master_spi[0].ctrl_on = 1;
break;
case 14:
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = IO14;
master_spi[0].ctrl_on = 1;
break;
case 15:
master_spi[0].ctrl_on = 1;
master_spi[0].cs_pin[0] = IO15;
master_spi[0].ctrl_on = 1;
break;
case 18:
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = IO18;
master_spi[1].ctrl_on = 1;
break;
case 19:
master_spi[1].ctrl_on = 1;
master_spi[1].cipo_pin = IO19;
master_spi[1].ctrl_on = 1;
break;
case 23:
master_spi[1].ctrl_on = 1;
master_spi[1].copi_pin = IO23;
master_spi[1].ctrl_on = 1;
break;
case 5:
master_spi[1].ctrl_on = 1;
master_spi[1].cs_pin[0] = IO5;
master_spi[1].ctrl_on = 1;
break;
}
break;
......@@ -1088,20 +1088,20 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
case 4:
switch (gpio) {
case 9:
master_uart[1].ctrl_on = 1;
master_uart[1].rx_pin = IO9;
master_uart[1].ctrl_on = 1;
break;
case 10:
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = IO10;
master_uart[1].ctrl_on = 1;
break;
case 16:
master_uart[2].ctrl_on = 1;
master_uart[2].rx_pin = IO16;
master_uart[2].ctrl_on = 1;
break;
case 17:
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = IO17;
master_uart[2].ctrl_on = 1;
break;
}
break;
......@@ -1111,7 +1111,7 @@ void cboard_DevKitC::PinsExtraConfig(int cfg) {
} break;
case QEMU_EXTRA_PIN_LEDC_CFG:
bitbang_pwm_set_duty(&ledc, (cfg & 0x0F00) >> 8, cfg & 0xFF);
bitbang_pwm_set_duty(&pwm_out, (cfg & 0x0F00) >> 8, cfg & 0xFF);
break;
}
}
......
src/boards/board_STM32_H103.cc
View file @ 82f69827
......@@ -45,6 +45,84 @@ enum {
O_RST // Reset button
};
// copied from qemu, must be the same
enum {
STM32_PERIPH_UNDEFINED = -1,
STM32_RCC_PERIPH = 0,
STM32_GPIOA,
STM32_GPIOB,
STM32_GPIOC,
STM32_GPIOD,
STM32_GPIOE,
STM32_GPIOF,
STM32_GPIOG,
STM32_GPIOH,
STM32_GPIOI,
STM32_GPIOJ,
STM32_GPIOK,
STM32_SYSCFG,
STM32_AFIO_PERIPH,
STM32_UART1,
STM32_UART2,
STM32_UART3,
STM32_UART4,
STM32_UART5,
STM32_UART6,
STM32_UART7,
STM32_UART8,
STM32_ADC1,
STM32_ADC2,
STM32_ADC3,
STM32_DAC,
STM32_TIM1,
STM32_TIM2,
STM32_TIM3,
STM32_TIM4,
STM32_TIM5,
STM32_TIM6,
STM32_TIM7,
STM32_TIM8,
STM32_TIM9,
STM32_TIM10,
STM32_TIM11,
STM32_TIM12,
STM32_TIM13,
STM32_TIM14,
STM32_BKP,
STM32_PWR,
STM32_I2C1,
STM32_I2C2,
STM32_I2C3,
STM32_I2S2,
STM32_I2S3,
STM32_WWDG,
STM32_IWDG,
STM32_CAN1,
STM32_CAN2,
STM32_CAN,
STM32_USB,
STM32_SPI1,
STM32_SPI2,
STM32_SPI3,
STM32_EXTI_PERIPH,
STM32_SDIO,
STM32_FSMC,
STM32_RTC,
STM32_COMP,
STM_LCD,
STM32_CRC,
STM32_DMA1,
STM32_DMA2,
STM32_DCMI_PERIPH,
STM32_CRYP_PERIPH,
STM32_HASH_PERIPH,
STM32_RNG_PERIPH,
STM32_FLASH,
STM32_FLASH_REGS,
STM32_PERIPH_COUNT,
};
#define A 0x1000
#define B 0x2000
#define C 0x3000
......@@ -118,6 +196,17 @@ static const short int pinmap[65] = {
-1 // 64 VDD
};
static unsigned char iopin(const unsigned short port, const unsigned int num) {
unsigned char pin = 0;
unsigned short value = port | num;
for (int i = 0; i < 65; i++) {
if (pinmap[i] == value) {
pin = i;
}
}
return pin;
}
const short int* cboard_STM32_H103::GetPinMap(void) {
return pinmap;
}
......@@ -191,6 +280,8 @@ cboard_STM32_H103::cboard_STM32_H103(void) {
master_uart[2].tx_pin = 0;
master_uart[2].rx_pin = 0;
bitbang_pwm_init(&pwm_out, this, 20);
if (PICSimLab.GetWindow()) {
// label1
label1 = new CLabel();
......@@ -230,6 +321,7 @@ cboard_STM32_H103::~cboard_STM32_H103(void) {
PICSimLab.GetWindow()->DestroyChild(label1);
PICSimLab.GetWindow()->DestroyChild(combo1);
}
bitbang_pwm_end(&pwm_out);
}
// Reset board status
......@@ -797,113 +889,396 @@ void cboard_STM32_H103::MSetAPin(int pin, float value) {
}
void cboard_STM32_H103::PinsExtraConfig(int cfg) {
if ((cfg & 0x8008) == 0x8008) { // Alternate function
int pin = (cfg & 0x7FF0) >> 4;
if ((cfg & 0xF00008) == 0x800008) { // Alternate function
int pin = (cfg & 0x0FF0) >> 4;
int port = cfg & 0x0003;
uint32_t* uart_afio;
uint32_t* afio;
// int cfg_ = (cfg & 0x000C) >> 2;
// printf("Extra CFG port(%i) pin[%02i]=0x%02X \n", port, pin, cfg_);
// printf("Extra CFG Alternate function port(%c) pin[%02i]=0x%02X \n", port + 'A', pin, cfg_);
switch (port) {
case 0: // GPIOA
switch (pin) {
case 2: // uart2
uart_afio = qemu_picsimlab_get_internals(0x1000 | 15);
if (!(*uart_afio)) {
case 0:
// tim2 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 0] = iopin(A, 0);
}
break;
case 1:
// tim2 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 1] = iopin(A, 1);
}
break;
case 2:
// uart2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART2);
if (!(*afio)) {
master_uart[1].tx_pin = iopin(A, 2);
master_uart[1].rx_pin = iopin(A, 3);
master_uart[1].ctrl_on = 1;
break;
}
// tim2 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 2] = iopin(A, 2);
}
break;
case 3:
// uart2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART2);
if (!(*afio)) {
master_uart[1].tx_pin = iopin(A, 2);
master_uart[1].rx_pin = iopin(A, 3);
master_uart[1].ctrl_on = 1;
master_uart[1].tx_pin = 16; // pa2
master_uart[1].rx_pin = 17; // pa3
break;
}
// tim2 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 0) {
pwm_out.pins[(1 << 2) + 3] = iopin(A, 3);
}
break;
case 4:
break;
case 5:
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
}
break;
case 6:
case 7: // spi1
uart_afio = qemu_picsimlab_get_internals(0x1000 | 53);
if (!(*uart_afio)) {
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = 21; // pa5
master_spi[0].copi_pin = 23; // pa7
master_spi[0].cipo_pin = 22; // pa6
break;
}
// tim3 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 0] = iopin(A, 6);
}
break;
case 9: // uart1
uart_afio = qemu_picsimlab_get_internals(0x1000 | 14);
if (!(*uart_afio)) {
case 7:
// spi1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(A, 5);
master_spi[0].copi_pin = iopin(A, 7);
master_spi[0].cipo_pin = iopin(A, 6);
master_spi[0].ctrl_on = 1;
break;
}
// tim1_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 7);
break;
}
// tim3 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 1] = iopin(A, 7);
}
break;
case 8:
// tim1 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 0] = iopin(A, 8);
}
break;
case 9:
// uart1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if (!(*afio)) {
master_uart[0].tx_pin = iopin(A, 9);
master_uart[0].rx_pin = iopin(A, 10);
master_uart[0].ctrl_on = 1;
break;
}
// tim1 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 1] = iopin(A, 9);
}
break;
case 10:
// uart1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if (!(*afio)) {
master_uart[0].tx_pin = iopin(A, 9);
master_uart[0].rx_pin = iopin(A, 10);
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = 42; // pa9
master_uart[0].rx_pin = 43; // pa10
break;
}
// tim1 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 2] = iopin(A, 10);
}
break;
case 11:
// tim1 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 0) {
pwm_out.pins[(0 << 2) + 3] = iopin(A, 11);
}
break;
case 12:
break;
case 13:
break;
case 14:
break;
case 15:
break;
}
break;
case 1: // GPIOB
switch (pin) {
case 0:
// tim1_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 1] = iopin(B, 0);
break;
}
// tim3_ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 2] = iopin(B, 0);
}
break;
case 1:
// tim1_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM1);
if (*afio == 1) {
pwm_out.pins[(0 << 2) + 2] = iopin(B, 1);
break;
}
// tim3_ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 0) {
pwm_out.pins[(2 << 2) + 3] = iopin(B, 1);
}
break;
case 2:
break;
case 3:
// tim2_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 1] = iopin(B, 3);
break;
}
case 4:
case 5: // spi1 (alt)
uart_afio = qemu_picsimlab_get_internals(0x1000 | 53);
if (!(*uart_afio)) {
// tim3_ch1n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 0] = iopin(B, 4);
break;
}
case 5:
// spi1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI1);
if (!(*afio)) {
master_spi[0].sck_pin = iopin(B, 3);
master_spi[0].copi_pin = iopin(B, 5);
master_spi[0].cipo_pin = iopin(B, 4);
master_spi[0].ctrl_on = 1;
master_spi[0].sck_pin = 55; // pb3
master_spi[0].copi_pin = 57; // pb5
master_spi[0].cipo_pin = 56; // pb4
break;
}
// tim3_ch2n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM3);
if (*afio == 2) {
pwm_out.pins[(2 << 2) + 1] = iopin(B, 5);
break;
}
break;
case 6: // uart1 (alt) and i2c
uart_afio = qemu_picsimlab_get_internals(0x1000 | 14);
if ((*uart_afio)) {
case 6:
// uart1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if ((*afio)) {
master_uart[0].tx_pin = iopin(B, 6);
master_uart[0].rx_pin = iopin(B, 7);
master_uart[0].ctrl_on = 1;
master_uart[0].tx_pin = 58; // pb6
master_uart[0].rx_pin = 59; // pb7
break;
}
// break;
case 7: // i2c0
uart_afio = qemu_picsimlab_get_internals(0x1000 | 42);
if (!(*uart_afio)) {
// i2c
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (!(*afio)) {
master_i2c[0].scl_pin = iopin(B, 6);
master_i2c[0].sda_pin = iopin(B, 7);
master_i2c[0].ctrl_on = 1;
break;
}
// tim4 ch1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 0] = iopin(B, 6);
}
break;
case 7:
// uart1 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART1);
if ((*afio)) {
master_uart[0].tx_pin = iopin(B, 6);
master_uart[0].rx_pin = iopin(B, 7);
master_uart[0].ctrl_on = 1;
break;
}
// i2c0
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (!(*afio)) {
master_i2c[0].scl_pin = iopin(B, 6);
master_i2c[0].sda_pin = iopin(B, 7);
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = 58; // pb6
master_i2c[0].sda_pin = 59; // pb7
break;
}
// tim4 ch2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 1] = iopin(B, 7);
}
break;
case 8:
case 9: // i2c0 (alt)
uart_afio = qemu_picsimlab_get_internals(0x1000 | 42);
if ((*uart_afio)) {
// i2c0 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if ((*afio)) {
master_i2c[0].scl_pin = iopin(B, 8);
master_i2c[0].sda_pin = iopin(B, 9);
master_i2c[0].ctrl_on = 1;
break;
}
// tim4 ch3
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 2] = iopin(B, 8);
}
case 9:
// i2c0 (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if ((*afio)) {
master_i2c[0].scl_pin = iopin(B, 8);
master_i2c[0].sda_pin = iopin(B, 9);
master_i2c[0].ctrl_on = 1;
master_i2c[0].scl_pin = 61; // pb8
master_i2c[0].sda_pin = 62; // pb9
break;
}
// tim4 ch4
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM4);
if (*afio == 0) {
pwm_out.pins[(3 << 2) + 3] = iopin(B, 9);
}
break;
case 10:
// tim2_ch3n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 2] = iopin(B, 10);
break;
case 10: // uart3
}
/*
uart_afio = qemu_picsimlab_get_internals(0x1000 | 16);
// uart3
uart_afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART3);
if (!(*uart_afio)) {
master_uart[2].tx_pin = iopin(B, 10);
master_uart[2].rx_pin = iopin(B, 11);
master_uart[2].ctrl_on = 1;
master_uart[2].tx_pin = 29; // pb10
master_uart[2].rx_pin = 30; // pb11
break
}
*/
case 11: // i2c1
// i2c1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (*afio == 0) {
master_i2c[1].scl_pin = iopin(B, 10);
master_i2c[1].sda_pin = iopin(B, 11);
master_i2c[1].ctrl_on = 1;
master_i2c[1].scl_pin = 29; // pb10
master_i2c[1].sda_pin = 30; // pb11
break;
}
break;
case 11:
// tim2_ch4n (alt)
afio = qemu_picsimlab_get_internals(0x1000 | STM32_TIM2);
if (*afio == 1) {
pwm_out.pins[(1 << 2) + 3] = iopin(B, 10);
break;
}
/*
// uart3
uart_afio = qemu_picsimlab_get_internals(0x1000 | STM32_UART3);
if (!(*uart_afio)) {
master_uart[2].tx_pin = iopin(B, 10);
master_uart[2].rx_pin = iopin(B, 11);
master_uart[2].ctrl_on = 1;
break;
}
*/
// i2c1
afio = qemu_picsimlab_get_internals(0x1000 | STM32_I2C1);
if (*afio == 0) {
master_i2c[1].scl_pin = iopin(B, 10);
master_i2c[1].sda_pin = iopin(B, 11);
master_i2c[1].ctrl_on = 1;
break;
}
break;
case 12:
break;
case 13:
case 14:
case 15: // spi2
case 15:
// spi2
afio = qemu_picsimlab_get_internals(0x1000 | STM32_SPI2);
if (*afio == 0) {
master_spi[1].sck_pin = iopin(B, 13);
master_spi[1].copi_pin = iopin(B, 15);
master_spi[1].cipo_pin = iopin(B, 14);
master_spi[1].ctrl_on = 1;
master_spi[1].sck_pin = 34; // pb13
master_spi[1].copi_pin = 36; // pb15
master_spi[1].cipo_pin = 35; // pb14
}
break;
}
break;
/*
case 2: // GPIOC
switch (pin) {
case 13:
break;
case 14:
break;
case 15:
break;
}
break;
case 3: // GPIOD
switch (pin) {
case 0:
break;
case 1:
break;
}
break;
*/
}
} else if ((cfg & 0xF00000) == 0xC00000) { // timer ccmr1 function
int duty = (cfg & 0xFFFF0) >> 4;
int chn = (cfg & 0x000C) >> 2;
int timer = cfg & 0x0003;
// printf("TIM %i chn %i dut set to %i\n", timer + 1, chn + 1, duty);
bitbang_pwm_set_duty(&pwm_out, (timer << 2) + chn, duty);
}
}
......
src/boards/bsim_qemu.cc
View file @ 82f69827
......@@ -1141,7 +1141,7 @@ void bsim_qemu::MReset(int flags) {
bitbang_uart_rst(&master_uart[0]);
bitbang_uart_rst(&master_uart[1]);
bitbang_uart_rst(&master_uart[2]);
bitbang_pwm_rst(&ledc);
bitbang_pwm_rst(&pwm_out);
}
const picpin* bsim_qemu::MGetPinsValues(void) {
......@@ -1204,10 +1204,10 @@ void bsim_qemu::MStep(void) {
}
}
}
for (int i = 0; i < ledc.chanels; i++) {
if (ledc.pins[i]) {
pins[ledc.pins[i] - 1].dir = PD_OUT;
pins[ledc.pins[i] - 1].value = ledc.out[i];
for (int i = 0; i < pwm_out.chanels; i++) {
if (pwm_out.pins[i]) {
pins[pwm_out.pins[i] - 1].dir = PD_OUT;
pins[pwm_out.pins[i] - 1].value = pwm_out.out[i];
}
}
}
......
src/boards/bsim_qemu.h
View file @ 82f69827
......@@ -72,7 +72,7 @@ public:
bitbang_i2c_t master_i2c[2];
bitbang_spi_t master_spi[2];
bitbang_uart_t master_uart[3];
bitbang_pwm_t ledc;
bitbang_pwm_t pwm_out;
void IoLockAccess(void) override;
void IoUnlockAccess(void) override;
int GetUARTRX(const int uart_num) override;
......
src/parts/output_LEDs.cc
View file @ 82f69827
......@@ -57,8 +57,6 @@ cpart_leds::cpart_leds(const unsigned x, const unsigned y, const char* name, con
OWidth = Width;
OHeight = Height;
ChangeSize(8);
input_pins[0] = 0;
input_pins[1] = 0;
input_pins[2] = 0;
......@@ -68,6 +66,8 @@ cpart_leds::cpart_leds(const unsigned x, const unsigned y, const char* name, con
input_pins[6] = 0;
input_pins[7] = 0;
ChangeSize(8);
colors[0] = 0;
colors[1] = 0;
colors[2] = 0;
......@@ -235,9 +235,11 @@ void cpart_leds::ReadPreferences(lxString value) {
void cpart_leds::RegisterRemoteControl(void) {
const picpin* ppins = SpareParts.GetPinsValues();
for (int i = 0; i > 8; i++) {
for (int i = 0; i < 8; i++) {
if (input_pins[i]) {
output_ids[O_L1 + i]->status = (void*)&ppins[input_pins[i] - 1].oavalue;
} else {
output_ids[O_L1 + i]->status = NULL;
}
}
}
......@@ -337,6 +339,7 @@ void cpart_leds::ChangeSize(const unsigned int sz) {
outputc = Size * 2;
LoadImage();
}
RegisterRemoteControl();
}
void cpart_leds::LoadImage(void) {
......
src/picsimlab5.cc
View file @ 82f69827
......@@ -93,6 +93,9 @@ void CPWindow5::_EvOnCreate(CControl* control) {
? (lxT("PICSimLab[") + itoa(PICSimLab.GetInstanceNumber()) + lxT("] - "))
: (lxT("PICSimLab - "))) +
"Spare parts");
msleep(BASETIMER);
PICSimLab.GetBoard()->Reset();
}
void CPWindow5::draw1_EvMouseButtonPress(CControl* control, uint button, uint x, uint y, uint state) {
......
tests/in_out/in_out/in_out.ino 0 → 100644
View file @ 82f69827
#if defined(ARDUINO_ARCH_AVR)
#define ADCMAX 1023
#define ANALOGIN A0
#define LED1 3
#define PBUTTON 2
#define LED2 4
#else
#endif
#if defined(ARDUINO_ARCH_STM32)
#define ADCMAX 1023
#define ANALOGIN PA0
#define LED1 PB1
#define PBUTTON PB3
#define LED2 PB4
#endif
#if defined(ARDUINO_ARCH_ESP32)
#if defined (CONFIG_IDF_TARGET_ESP32C3)
#define ADCMAX 4095
#define ANALOGIN 0
#define LED1 1
#define PBUTTON 3
#define LED2 4
#else
#define ADCMAX 4095
#define ANALOGIN 4
#define LED1 3
#define PBUTTON 2
#define LED2 5
#endif
#endif
static int bstate = 0;
void isr(void) {
bstate = digitalRead(PBUTTON);
}
void setup() {
Serial.begin(115200);
pinMode(ANALOGIN, INPUT);
pinMode(PBUTTON , INPUT_PULLUP);
pinMode(LED1, OUTPUT);
pinMode(LED2, OUTPUT);
digitalWrite(LED1, LOW);
digitalWrite(LED2, LOW);
attachInterrupt(digitalPinToInterrupt(PBUTTON), isr, CHANGE);
}
unsigned int value;
unsigned char value2;
char buffer[50];
void loop() {
value = analogRead(ANALOGIN);
value2 = map(value, 0 , ADCMAX, 0, 255 );
analogWrite(LED1, value2);
digitalWrite(LED2, bstate);
sprintf(buffer, "AD=%04d PWM=%03d BT=%d", value, value2, bstate);
Serial.println(buffer);
delay(250);
}
tests/test_in_out.cc 0 → 100644
View file @ 82f69827
/* ########################################################################
PICsimLab - PIC laboratory simulator
########################################################################
Copyright (c) : 2020-2023 Luis Claudio Gamboa Lopes
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
For e-mail suggestions : lcgamboa@yahoo.com
######################################################################## */
#include <stdio.h>
#include <string.h>
#include <unistd.h>
#include "tests.h"
static int in_out_test(const char* tname, const char* fname, const int start_delay_sec = 1,
const unsigned long inter_delay_us = 1000000L) {
int pwm;
int state;
printf("test %s\n", tname);
if (!test_load(fname)) {
return 0;
}
sleep(start_delay_sec);
for (int i = 0; i < 3; i++) {
if (!test_send_rcmd("set part[02].in[00] 1")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
usleep(inter_delay_us);
if (!test_send_rcmd("get part[01].out[03]")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
sscanf(test_get_cmd_resp() + 22, "%i", &state);
if (state < 50) {
printf("Failed in Button Test \n");
test_end();
return 0;
}
if (!test_send_rcmd("set part[02].in[00] 0")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
usleep(inter_delay_us);
if (!test_send_rcmd("get part[01].out[03]")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
sscanf(test_get_cmd_resp() + 22, "%i", &state);
if (state > 150) {
printf("Failed in Button Test \n");
test_end();
return 0;
}
}
for (int i = 0; i < 3; i++) {
if (!test_send_rcmd("set part[00].in[00] 0")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
usleep(inter_delay_us);
if (!test_send_rcmd("get part[01].out[01]")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
sscanf(test_get_cmd_resp() + 22, "%i", &pwm);
if (pwm > 5) {
printf("Failed in PWM Test Set 0 Get %i\n", pwm);
test_end();
return 0;
}
if (!test_send_rcmd("set part[00].in[00] 100")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
usleep(inter_delay_us);
if (!test_send_rcmd("get part[01].out[01]")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
sscanf(test_get_cmd_resp() + 22, "%i", &pwm);
if ((pwm < 95) || (pwm > 105)) {
printf("Failed in PWM Test Set 100 Get %i\n", pwm);
test_end();
return 0;
}
if (!test_send_rcmd("set part[00].in[00] 200")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
usleep(inter_delay_us);
if (!test_send_rcmd("get part[01].out[01]")) {
printf("Error send rcmd \n");
test_end();
return 0;
}
sscanf(test_get_cmd_resp() + 22, "%i", &pwm);
if (pwm < 195) {
printf("Failed in PWM Test Set 200 Get %i\n", pwm);
test_end();
return 0;
}
}
return test_end();
}
static int test_IN_OUT_ESP32(void* arg) {
return in_out_test("SPI ESP32", "in_out/in_out_esp32.pzw", 5);
}
register_test("IN/OUT ESP32", test_IN_OUT_ESP32, NULL);
static int test_IN_OUT_ESP32C3(void* arg) {
return in_out_test("SPI ESP32C3", "in_out/in_out_esp32c3.pzw", 1, 2000000L);
}
register_test("IN/OUT ESP32C3", test_IN_OUT_ESP32C3, NULL);
static int test_IN_OUT_AVR(void* arg) {
return in_out_test("SPI AVR", "in_out/in_out_uno.pzw");
}
register_test("IN/OUT AVR", test_IN_OUT_AVR, NULL);
static int test_IN_OUT_STM32(void* arg) {
return in_out_test("SPI STM32", "in_out/in_out_stm32.pzw", 1, 2000000L);
}
register_test("IN/OUT STM32", test_IN_OUT_STM32, NULL);
/*
static int test_IN_OUT_PIC18F(void* arg) {
return in_out_test("SPI PIC18F", "in_out/in_out_p18.pzw");
}
register_test("IN/OUT PIC18F", test_IN_OUT_PIC18F, NULL);
*/
\ No newline at end of file
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