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xpstem
micropython
Commits
39bc430e
Commit
39bc430e
authored
Dec 20, 2019
by
Damien George
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tests/pyb: Adjust UART and Timer tests to work on PYBD_SF6.
parent
073c5f3a
Changes
3
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3 changed files
with
2 additions
and
3 deletions
+2
-3
tests/pyb/timer.py
tests/pyb/timer.py
+1
-1
tests/pyb/uart.py
tests/pyb/uart.py
+1
-1
tests/pyb/uart.py.exp
tests/pyb/uart.py.exp
+0
-1
No files found.
tests/pyb/timer.py
View file @
39bc430e
...
...
@@ -16,4 +16,4 @@ print(tim.period())
tim
=
Timer
(
2
,
freq
=
100
)
print
(
tim
.
freq
())
tim
.
freq
(
0.001
)
print
(
tim
.
freq
(
))
print
(
'{:.3f}'
.
format
(
tim
.
freq
()
))
tests/pyb/uart.py
View file @
39bc430e
from
pyb
import
UART
# test we can correctly create by id
for
bus
in
(
-
1
,
0
,
1
,
2
,
5
,
6
,
7
):
for
bus
in
(
-
1
,
0
,
1
,
2
,
5
,
6
):
try
:
UART
(
bus
,
9600
)
print
(
"UART"
,
bus
)
...
...
tests/pyb/uart.py.exp
View file @
39bc430e
...
...
@@ -4,7 +4,6 @@ UART 1
UART 2
ValueError 5
UART 6
ValueError 7
UART(1, baudrate=9600, bits=8, parity=None, stop=1, flow=0, timeout=0, timeout_char=3, rxbuf=64)
UART(1, baudrate=2400, bits=8, parity=None, stop=1, flow=0, timeout=0, timeout_char=7, rxbuf=64)
0
...
...
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