uboot: version release v4.1.4

support u-boot-spl
[panel]add st7785m panel in uboot, sync clk with kernel
[fix](sbi size): get sbi size from memmap.h
[ion] support get ion total size

Change-Id: I108fdbd39646db2b70e8ef118622737806ce46d7

u-boot-2021.10/Kconfig

@@ -360,8 +360,8 @@ config BUILD_TARGET
 	default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
 	default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
 	default "u-boot-elf.srec" if RCAR_GEN3
-	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
-				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
+#	default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \
+#				ARCH_SUNXI || RISCV || ARCH_ZYNQMP)
 	default "u-boot.kwb" if ARCH_KIRKWOOD
 	default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT
 	default "u-boot-with-spl.imx" if ARCH_MX6 && SPL

u-boot-2021.10/arch/riscv/cpu/generic/Kconfig

@@ -4,7 +4,7 @@
 
 config GENERIC_RISCV
 	bool
-	select BINMAN if SPL
+#	select BINMAN if SPL
 	select ARCH_EARLY_INIT_R
 	imply CPU
 	imply CPU_RISCV

u-boot-2021.10/arch/riscv/cpu/u-boot-spl.lds

@@ -7,9 +7,10 @@
  * and arch/mips/cpu/u-boot-spl.lds.
  */
 MEMORY { .spl_mem : ORIGIN = IMAGE_TEXT_BASE, LENGTH = IMAGE_MAX_SIZE }
+/*
 MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
 		    LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
-
+*/
 OUTPUT_ARCH("riscv")
 ENTRY(_start)
 
@@ -79,5 +80,5 @@ SECTIONS
 		*(.bss*)
 		. = ALIGN(8);
 		__bss_end = .;
-	} > .bss_mem
+	} > .spl_mem
 }

u-boot-2021.10/arch/riscv/include/asm/boot0.h

@@ -12,7 +12,11 @@
 	.word 0x33334c42  /* b'BL33' */
 	.word 0xdeadbeea  /* CKSUM */
 	.word 0xdeadbeeb  /* SIZE */
-	.quad CONFIG_SYS_TEXT_BASE /* RUNADDR */
+#ifdef CONFIG_SPL_BUILD
+	.quad	CONFIG_SPL_TEXT_BASE
+#else
+	.quad   CONFIG_SYS_TEXT_BASE
+#endif
 	.word 0xdeadbeec
 	.balign 4
 	j boot0_time_recode

u-boot-2021.10/arch/riscv/lib/fdt_fixup.c

@@ -164,10 +164,11 @@ int arch_fixup_fdt(void *blob)
 		return log_msg_ret("could not set boot-hartid", err);
 #endif
 
+#ifndef CONFIG_SPL_BUILD
 	/* Copy the reserved-memory node to the DT used by OS */
 	err = riscv_fdt_copy_resv_mem_node(gd->fdt_blob, blob);
 	if (err < 0)
 		return err;
-
+#endif
 	return 0;
 }

u-boot-2021.10/board/cvitek/Kconfig

@@ -24,6 +24,7 @@ config TARGET_CVITEK_CV181X
 config TARGET_CVITEK_CV180X
 	bool "Support CVITEK CV180X"
 	select TARGET_CVITEK
+
 endchoice
 
 source "board/cvitek/cv1835/Kconfig"

u-boot-2021.10/board/k+p/bootscripts/tpcboot.cmd

-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018
-# Lukasz Majewski, DENX Software Engineering, lukma@denx.de
-# This is an example file to generate boot.scr - a boot script for U-Boot
-# Generate boot.scr:
-# ./tools/mkimage -c none -A arm -T script -d tpcboot.cmd boot.scr
-#
-
-
-# Input envs (to be set in environment)
-# Mandatory:
-# kernel_file = "fitImage"
-# boardname = "XXXX"  // set automatically in u-boot
-# boardsoc = "imx6q"  // set automatically in u-boot
-#
-# Optional:
-# bootcmd_force = "nfs" "tftp_kernel"
-# If not set - eMMC/SD boot
-
-# Generic setup
-setenv mmcroot "/dev/mmcblk${devnum}p2 rootwait rw"
-setenv displayargs ""
-setenv mmcargs "setenv bootargs console=${console} ${smp} root=${mmcroot} \
-	${displayargs}"
-setenv miscadj "
-if test '${boardsoc}' = 'imx53'; then
-       setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
-fi;"
-setenv nfsadj "
-if test '${boardsoc}' = 'imx53'; then
-   if test '${boardtype}' = 'hsc'; then
-       setenv bootargs '${bootargs} dsa_core.blacklist=yes';
-   fi;
-fi;"
-setenv boot_fitImage "
-	setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
-	setenv itbcfg "\"#\${fdt_conf}\"";
-	print itbcfg;
-	bootm '${loadaddr}${itbcfg}';"
-
-#------------------------------------------------------------
-#
-# Provide default 'bootcmd' command
-#------------------------------------------------------------
-setenv bootcmd "
-if test -e ${devtype} ${devnum}:${distro_bootpart} ${kernel_file}; then
-	echo Found kernel image: ${kernel_file};
-	if load ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} \
-	   ${kernel_file}; then
-		run mmcargs;
-		run miscadj;
-		run boot_fitImage;
-	fi;
-fi;"
-
-#------------------------------------------------------------
-#
-# Provide 'boot_tftp_kernel' command
-#------------------------------------------------------------
-setenv download_kernel "dhcp ${loadaddr} ${kernel_file}"
-
-setenv boot_tftp_kernel "
-if run download_kernel; then
-	run mmcargs;
-	run miscadj;
-	run boot_fitImage;
-fi"
-
-#------------------------------------------------------------
-#
-# Provide 'boot_nfs' command
-#------------------------------------------------------------
-setenv nfsargs "setenv bootargs root=/dev/nfs rw nfsroot='${rootpath}',nolock,nfsvers=3"
-setenv addip "setenv bootargs '${bootargs}' ip='${ipaddr}':'${serverip}':'${gatewayip}':'${netmask}':'${hostname}':eth0:on"
-
-setenv boot_nfs "
-if run download_kernel; then
-	run nfsargs;
-	run addip;
-	run nfsadj;
-	setenv bootargs '${bootargs}' console=${console};
-
-	run boot_fitImage;
-fi"
-
-#------------------------------------------------------------
-#
-# Set correct boot flow
-#------------------------------------------------------------
-
-setenv bcmd "
-if test ! -n ${bootcmd_force}; then
-	run bootcmd;
-fi;
-if test ${bootcmd_force} = nfs; then
-	run boot_nfs;
-else if test ${bootcmd_force} = tftp_kernel; then
-	run boot_tftp_kernel;
-     fi;
-fi"
-
-run bcmd

u-boot-2021.10/board/samsung/common/bootscripts/autoboot.cmd

-# This is an example file to generate boot.scr - a boot script for U-Boot
-# Generate boot.scr:
-# ./tools/mkimage -c none -A arm -T script -d autoboot.cmd boot.scr
-#
-# It requires a list of environment variables to be defined before load:
-# platform dependent: board_name, fdtfile, console
-# system dependent: mmcbootdev, mmcbootpart, mmcrootdev, mmcrootpart, rootfstype
-#
-setenv fdtaddr     "40800000"
-setenv initrdname  "uInitrd"
-setenv initrdaddr  "42000000"
-setenv loaddtb     "load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} ${fdtfile}"
-setenv loadinitrd  "load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} ${initrdname}"
-setenv loadkernel  "load mmc ${mmcbootdev}:${mmcbootpart} '${kerneladdr}' '${kernelname}'"
-setenv kernel_args "setenv bootargs ${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}"
-
-#### Routine: check_dtb - check that target.dtb exists on boot partition
-setenv check_dtb "
-if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${fdtfile}'; then
-	run loaddtb;
-	setenv fdt_addr ${fdtaddr};
-else
-	echo Warning! Booting without DTB: '${fdtfile}'!;
-	setenv fdt_addr;
-fi;"
-
-#### Routine: check_ramdisk - check that uInitrd exists on boot partition
-setenv check_ramdisk "
-if test -e mmc '${mmcbootdev}':'${mmcbootpart}' '${initrdname}'; then
-	echo "Found ramdisk image.";
-	run loadinitrd;
-	setenv initrd_addr ${initrdaddr};
-else
-	echo Warning! Booting without RAMDISK: '${initrdname}'!;
-	setenv initrd_addr -;
-fi;"
-
-#### Routine: boot_fit - check that env $board_name is set and boot proper config of ITB image
-setenv setboot_fit "
-if test -e '${board_name}'; then
-	setenv fdt_addr ;
-	setenv initrd_addr ;
-	setenv kerneladdr  0x42000000;
-	setenv kernelname  Image.itb;
-	setenv itbcfg      "\"#${board_name}\"";
-	setenv imgbootcmd  bootm;
-else
-	echo Warning! Variable: \$board_name is undefined!;
-fi"
-
-#### Routine: setboot_uimg - prepare env to boot uImage
-setenv setboot_uimg "
-	setenv kerneladdr 0x40007FC0;
-	setenv kernelname uImage;
-	setenv itbcfg     ;
-	setenv imgbootcmd bootm;
-	run check_dtb;
-	run check_ramdisk;"
-
-#### Routine: setboot_zimg - prepare env to boot zImage
-setenv setboot_zimg "
-	setenv kerneladdr 0x40007FC0;
-	setenv kernelname zImage;
-	setenv itbcfg     ;
-	setenv imgbootcmd bootz;
-	run check_dtb;
-	run check_ramdisk;"
-
-#### Routine: boot_img - boot the kernel after env setup
-setenv boot_img "
-	run loadkernel;
-	run kernel_args;
-	'${imgbootcmd}' '${kerneladdr}${itbcfg}' '${initrd_addr}' '${fdt_addr}';"
-
-#### Routine: autoboot - choose proper boot path
-setenv autoboot "
-if test -e mmc ${mmcbootdev}:${mmcbootpart} Image.itb; then
-	echo Found kernel image: Image.itb;
-	run setboot_fit;
-	run boot_img;
-elif test -e mmc ${mmcbootdev}:${mmcbootpart} zImage; then
-	echo Found kernel image: zImage;
-	run setboot_zimg;
-	run boot_img;
-elif test -e mmc ${mmcbootdev}:${mmcbootpart} uImage; then
-	echo Found kernel image: uImage;
-	run setboot_uimg;
-	run boot_img;
-fi;"
-
-#### Execute the defined autoboot macro
-run autoboot

u-boot-2021.10/board/samsung/common/bootscripts/bootzimg.cmd

-setenv kernelname zImage;
-setenv boot_kernel "setenv bootargs \"${console} root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} rootfstype=${rootfstype} rootwait ${opts}\";
-load mmc ${mmcbootdev}:${mmcbootpart} 0x40007FC0 '${kernelname}';
-if load mmc ${mmcbootdev}:${mmcbootpart} 40800000 ${fdtfile}; then
-	bootz 0x40007FC0 - 40800000;
-else
-	echo Warning! Booting without DTB: '${fdtfile}'!;
-	bootz 0x40007FC0 -;
-fi;"
-run boot_kernel;
\ No newline at end of file

u-boot-2021.10/board/xilinx/bootscripts/qspiboot.cmd

-# This is an example file to generate boot.scr - a boot script for U-Boot
-# This example only target for qspi boot, sameway it can be created for boot
-# devices like nand.
-# Generate boot.scr:
-# ./tools/mkimage -c none -A arm -T script -d qspiboot.cmd boot.scr
-#
-# It requires a list of environment variables to be defined before load:
-# fdt_addr, fdt_offset, fdt_size, kernel_addr, kernel_offset, kernel_size
-#
-sf probe 0 0 0 && sf read $fdt_addr $fdt_offset $fdt_size && sf read $kernel_addr $kernel_offset $kernel_size && booti $kernel_addr - $fdt_addr

u-boot-2021.10/board/xilinx/bootscripts/sdboot.cmd

-# This is an example file to generate boot.scr - a boot script for U-Boot
-# This example only target for qspi boot, sameway it can be created for boot
-# devices like nand.
-# Generate boot.scr:
-# ./tools/mkimage -c none -A arm -T script -d sdboot.cmd boot.scr
-#
-# It requires a list of environment variables used below to be defined
-# before load
-#
-mmc dev $devnum && mmcinfo && run uenvboot || run sdroot$devnum;load mmc $devnum:$partid $fdt_addr system.dtb && load mmc $devnum:$partid $kernel_addr Image && booti $kernel_addr - $fdt_addr

u-boot-2021.10/cmd/cvi_update.c

@@ -93,8 +93,9 @@ int _prgImage(char *file, uint32_t chunk_header_size, char *file_name)
 	snprintf(cmd, 255, "nand write %p 0x%x 0x%x",
 		 (void *)file + chunk_header_size, offset, size);
 #elif defined(CONFIG_SPI_FLASH)
-	if (update_magic == SD_UPDATE_MAGIC && (!strcmp(file_name, "fip.bin") ||
-						!strcmp(file_name, "boot.spinor"))) {
+	if (update_magic == SD_UPDATE_MAGIC && (!strcmp(file_name, "fip_spl.bin")
+		|| !strcmp(file_name, "fip.bin")
+		|| !strcmp(file_name, "boot.spinor"))) {
 		snprintf(cmd, 255, "sf update %p 0x%x 0x%x",
 			 (void *)file + chunk_header_size, offset, size);
 	} else {
@@ -180,6 +181,7 @@ static int _storage_update(enum storage_type_e type)
 	char cmd[255] = { '\0' };
 	char strStorage[10] = { '\0' };
 	uint8_t sd_index = 0;
+	uint8_t fip_name[16] = {0};
 
 	if (type == sd_dl) {
 		printf("Start SD downloading...\n");
@@ -193,8 +195,13 @@ static int _storage_update(enum storage_type_e type)
 #endif
 		snprintf(cmd, 255, "mmc dev %u:1 SD_HS", sd_index);
 		run_command(cmd, 0);
-		snprintf(cmd, 255, "fatload %s %p fip.bin;", strStorage,
-			 (void *)HEADER_ADDR);
+#if defined(CONFIG_SPL)
+		strcpy(fip_name, "fip_spl.bin");
+#else
+		strcpy(fip_name, "fip.bin");
+#endif
+		snprintf(cmd, 255, "fatload %s %p %s;", strStorage,
+			 (void *)HEADER_ADDR, fip_name);
 		ret = run_command(cmd, 0);
 		if (ret) {
 			// Consider SD card without MBR
@@ -208,8 +215,8 @@ static int _storage_update(enum storage_type_e type)
 #endif
 			snprintf(cmd, 255, "mmc dev %u:0 SD_HS", sd_index);
 			run_command(cmd, 0);
-			snprintf(cmd, 255, "fatload %s %p fip.bin;", strStorage,
-				 (void *)HEADER_ADDR);
+			snprintf(cmd, 255, "fatload %s %p %s;", strStorage,
+				 (void *)HEADER_ADDR, fip_name);
 			ret = run_command(cmd, 0);
 			if (ret)
 				return ret;

u-boot-2021.10/common/common_fit.c

@@ -68,10 +68,10 @@ int fit_find_config_node(const void *fdt)
 				dflt_conf_desc = name;
 			}
 		}
-
+#ifndef CONFIG_SPL_BUILD
 		if (board_fit_config_name_match(name))
 			continue;
-
+#endif
 		debug("Selecting config '%s'\n", name);
 
 		return node;

u-boot-2021.10/common/fdt_support.c

@@ -19,6 +19,7 @@
 #include <fdt_support.h>
 #include <exports.h>
 #include <fdtdec.h>
+#include <linux/stringify.h>
 
 /**
  * fdt_getprop_u32_default_node - Return a node's property or a default
@@ -292,9 +293,11 @@ int fdt_chosen(void *fdt)
 	nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
 	if (nodeoffset < 0)
 		return nodeoffset;
-
+#ifdef CONFIG_SPL_BUILD
+	str = CVI_SPL_BOOTAGRS;
+#else
 	str = board_fdt_chosen_bootargs();
-
+#endif
 	if (str) {
 		err = fdt_setprop(fdt, nodeoffset, "bootargs", str,
 				  strlen(str) + 1);

u-boot-2021.10/common/malloc_simple.c

@@ -23,10 +23,10 @@ static void *alloc_simple(size_t bytes, int align)
 
 	addr = ALIGN(gd->malloc_base + gd->malloc_ptr, align);
 	new_ptr = addr + bytes - gd->malloc_base;
-	log_debug("size=%zx, ptr=%lx, limit=%lx: ", bytes, new_ptr,
-		  gd->malloc_limit);
+
 	if (new_ptr > gd->malloc_limit) {
-		log_err("alloc space exhausted\n");
+		log_err("alloc space exhausted\n"
+			"size=%lx, ptr=%lx, limit=%lx\n", bytes, new_ptr, gd->malloc_limit);
 		return NULL;
 	}
 

u-boot-2021.10/common/spl/Kconfig

 menu "SPL / TPL"
 
 config SUPPORT_SPL
-	bool
+	bool "SUPPORT_SPL"
 
 config SUPPORT_TPL
 	bool
@@ -34,12 +34,13 @@ config SPL_FRAMEWORK_BOARD_INIT_F
 	  - initialize the serial (preloader_console_init)
 	  Unless you want to provide your own board_init_f, you should say Y.
 
+# Don't use here, use the value from memmap.py
 config SPL_SIZE_LIMIT
-	hex "Maximum size of SPL image"
+#	hex "Maximum size of SPL image"
 	depends on SPL
 	default 0x11000 if ARCH_MX6 && !MX6_OCRAM_256KB
 	default 0x31000 if ARCH_MX6 && MX6_OCRAM_256KB
-	default 0x0
+#	default 0x0
 	help
 	  Specifies the maximum length of the U-Boot SPL image.
 	  If this value is zero, it is ignored.
@@ -156,14 +157,15 @@ config SPL_LDSCRIPT
 	  U-Boot stage.	 Set this to the path of the linker-script to
 	  be used for SPL.
 
+# Don't use here, use the value from memmap.py
 config SPL_TEXT_BASE
-	hex "SPL Text Base"
+#	hex "SPL Text Base"
 	default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
 	default 0x20060 if SUN50I_GEN_H6
 	default 0x00060 if ARCH_SUNXI
 	default 0xfffc0000 if ARCH_ZYNQMP
-	default 0x0
+#	default 0x0
 	help
 	  The address in memory that SPL will be running from.
 
@@ -918,9 +920,9 @@ config SPL_OS_BOOT
 	  for more info read doc/README.falcon
 
 if SPL_OS_BOOT
+# Don't use here, use the value from memmap.py
 config SYS_OS_BASE
-	hex "addr, where OS is found"
-	depends on SPL_NOR_SUPPORT
+	default 0x10100000 if SPL_NOR_SUPPORT
 	help
 	  Specify the address, where the OS image is found, which
 	  gets booted.

u-boot-2021.10/common/spl/spl.c

@@ -87,10 +87,11 @@ __weak int dram_init_banksize(void)
 #ifdef CONFIG_SPL_OS_BOOT
 __weak int spl_start_uboot(void)
 {
-	puts(SPL_TPL_PROMPT
-	     "Please implement spl_start_uboot() for your board\n");
-	puts(SPL_TPL_PROMPT "Direct Linux boot not active!\n");
-	return 1;
+	// puts(SPL_TPL_PROMPT
+	//      "Please implement spl_start_uboot() for your board\n");
+	// puts(SPL_TPL_PROMPT "Direct Linux boot not active!\n");
+	// return 1;
+	return 0;
 }
 
 /*
@@ -165,6 +166,22 @@ ulong spl_get_image_text_base(void)
 __weak void spl_board_prepare_for_linux(void)
 {
 	/* Nothing to do! */
+	cleanup_before_linux();
+}
+
+__weak void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
+{
+	typedef void (*image_entry_arg_t)(ulong, void *) __attribute__ ((noreturn));
+	image_entry_arg_t image_entry = (image_entry_arg_t)spl_image->entry_point;
+	// Save kernel start time
+	board_save_time_record(TIME_RECORDS_FIELD_KERNEL_START);
+#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
+	debug("flags=%d, entry_point=0x%lx, fdt_addr=0x%p\n",
+		spl_image->flags, spl_image->entry_point, spl_image->fdt_addr);
+	image_entry(0, spl_image->fdt_addr);
+#else
+	image_entry(spl_image->flags,  0);
+#endif
 }
 
 __weak void spl_board_prepare_for_optee(void *fdt)
@@ -556,7 +573,8 @@ int spl_init(void)
 
 __weak void board_boot_order(u32 *spl_boot_list)
 {
-	spl_boot_list[0] = spl_boot_device();
+	// spl_boot_list[0] = spl_boot_device();
+	 spl_boot_list[0] = BOOT_DEVICE_NOR;
 }
 
 static struct spl_image_loader *spl_ll_find_loader(uint boot_device)
@@ -627,7 +645,7 @@ static int boot_from_devices(struct spl_image_info *spl_image,
 		    CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) &&
 		    !IS_ENABLED(CONFIG_SILENT_CONSOLE)) {
 			if (loader)
-				printf("Trying to boot from %s\n",
+				debug("Trying to boot from %s\n",
 				       spl_loader_name(loader));
 			else if (CONFIG_IS_ENABLED(SHOW_ERRORS))
 				printf(SPL_TPL_PROMPT
@@ -647,6 +665,15 @@ static int boot_from_devices(struct spl_image_info *spl_image,
 #if defined(CONFIG_SPL_FRAMEWORK_BOARD_INIT_F)
 void board_init_f(ulong dummy)
 {
+	board_save_time_record(TIME_RECORDS_FIELD_UBOOT_START);
+#ifdef CONFIG_ARM64
+	extern ulong __image_copy_start;
+	gd->relocaddr = (ulong)&__image_copy_start;
+	arch_reserve_mmu();
+	icache_enable();
+	dcache_enable();
+	debug("%s : %d  cache enable\n", __func__, __LINE__);
+#endif
 	if (CONFIG_IS_ENABLED(OF_CONTROL)) {
 		int ret;
 
@@ -676,6 +703,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	debug(">>" SPL_TPL_PROMPT "board_init_r()\n");
 
 	spl_set_bd();
+	board_init();
 
 #if defined(CONFIG_SYS_SPL_MALLOC_START)
 	mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
@@ -683,9 +711,10 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	gd->flags |= GD_FLG_FULL_MALLOC_INIT;
 #endif
 	if (!(gd->flags & GD_FLG_SPL_INIT)) {
-		if (spl_init())
+		if (spl_init()) {
 			hang();
 		}
+	}
 #if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
 	/*
 	 * timer_init() does not exist on PPC systems. The timer is initialized
@@ -720,12 +749,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 	initr_watchdog();
 #endif
 
-	if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) ||
-	    IS_ENABLED(CONFIG_SPL_ATF))
-		dram_init_banksize();
+//	if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) ||
+//		IS_ENABLED(CONFIG_SPL_ATF))
+//			dram_init_banksize();
 
 	bootcount_inc();
-
+	board_save_time_record(TIME_RECORDS_FIELD_BOOTCMD_START);
 	memset(&spl_image, '\0', sizeof(spl_image));
 #ifdef CONFIG_SYS_SPL_ARGS_ADDR
 	spl_image.arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;

u-boot-2021.10/common/spl/spl_fit.c

@@ -17,6 +17,10 @@
 #include <asm/cache.h>
 #include <asm/global_data.h>
 #include <linux/libfdt.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+#include <lz4.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -258,7 +262,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 			debug("%s ", genimg_get_type_name(type));
 	}
 
-	if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+	if (IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA) || IS_ENABLED(CONFIG_SPL_LZ4)) {
 		fit_image_get_comp(fit, node, &image_comp);
 		debug("%s ", genimg_get_comp_name(image_comp));
 	}
@@ -330,6 +334,19 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 			return -EIO;
 		}
 		length = size;
+	} else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+		__maybe_unused SizeT lzma_len = 0x4000000;
+		if (lzmaBuffToBuffDecompress((void *)load_ptr, &lzma_len, src, length)) {
+			printf("error [%s : %d] load_ptr=0x%p, lzma_len=0x%lx, src=0x%p, length=0x%lx\n",
+				__func__, __LINE__, load_ptr, lzma_len, src, length);
+		}
+		length = lzma_len;
+	} else if (IS_ENABLED(CONFIG_SPL_LZ4) && image_comp == IH_COMP_LZ4) {
+		size_t lz4_len = 0x4000000;
+		if (ulz4fn(src, length, (void *)load_ptr, &lz4_len)) {
+			printf("error [%s : %d] load_ptr=0x%p, lz4_len=0x%lx, src=0x%p, length=0x%lx\n",
+				__func__, __LINE__, load_ptr, lz4_len, src, length);
+		}
 	} else {
 		memcpy(load_ptr, src, length);
 	}
@@ -346,6 +363,8 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector,
 			image_info->entry_point = FDT_ERROR;
 	}
 
+	// lmb_reserve(&images->lmb, images->os.load, (load_end -
+	// 					    images->os.load));
 	return 0;
 }
 
@@ -361,6 +380,94 @@ static bool os_takes_devicetree(uint8_t os)
 	}
 }
 
+
+static int spl_image_setup_libfdt(struct spl_image_info image_info, const struct spl_fit_info *ctx)
+{
+	bootm_headers_t images;
+	void *blob = (void *)image_info.load_addr;
+	int of_size = image_info.size;
+	debug("error ctx->fit=0x%p, of_size=0x%x, image_info->size=0x%x\n", blob, of_size, image_info.size);
+	struct lmb *lmb;
+	images.initrd_start = 0;
+	images.initrd_end = 0;
+
+	ulong *initrd_start = &images.initrd_start;
+	ulong *initrd_end = &images.initrd_end;
+	int ret = -EPERM;
+	int fdt_ret;
+
+	if (fdt_chosen(blob) < 0) {
+		printf("ERROR: /chosen node create failed\n");
+		goto err;
+	}
+
+	if (arch_fixup_fdt(blob) < 0) {
+		printf("ERROR: arch-specific fdt fixup failed\n");
+		goto err;
+	}
+
+	/* Update ethernet nodes */
+	// fdt_fixup_ethernet(blob);
+#if CONFIG_IS_ENABLED(CMD_PSTORE)
+	/* Append PStore configuration */
+	fdt_fixup_pstore(blob);
+#endif
+
+	if (IMAGE_OF_BOARD_SETUP) {
+		const char *skip_board_fixup;
+
+		skip_board_fixup = env_get("skip_board_fixup");
+		if (skip_board_fixup && ((int)simple_strtol(skip_board_fixup, NULL, 10) == 1)) {
+			printf("skip board fdt fixup\n");
+		} else {
+			fdt_ret = ft_board_setup(blob, gd->bd);
+			if (fdt_ret) {
+				printf("ERROR: board-specific fdt fixup failed: %s\n",
+				       fdt_strerror(fdt_ret));
+				goto err;
+			}
+		}
+	}
+
+	if (IMAGE_OF_SYSTEM_SETUP) {
+		fdt_ret = ft_system_setup(blob, gd->bd);
+		if (fdt_ret) {
+			printf("ERROR: system-specific fdt fixup failed: %s\n",
+			       fdt_strerror(fdt_ret));
+			goto err;
+		}
+	}
+
+	/* Delete the old LMB reservation */
+	if (lmb)
+		lmb_free(lmb, (phys_addr_t)(u32)(uintptr_t)blob,
+			 (phys_size_t)fdt_totalsize(blob));
+
+	ret = fdt_shrink_to_minimum(blob, 0);
+	if (ret < 0)
+		goto err;
+	of_size = ret;
+
+	/* Create a new LMB reservation */
+	if (lmb)
+		lmb_reserve(lmb, (ulong)blob, of_size);
+
+	fdt_initrd(blob, *initrd_start, *initrd_end);
+	if (!ft_verify_fdt(blob))
+		goto err;
+
+#if defined(CONFIG_SOC_KEYSTONE)
+	if (IMAGE_OF_BOARD_SETUP)
+		ft_board_setup_ex(blob, gd->bd);
+#endif
+
+	return 0;
+err:
+	printf(" - must RESET the board to recover.\n\n");
+
+	return ret;
+}
+
 static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 			      struct spl_load_info *info, ulong sector,
 			      const struct spl_fit_info *ctx)
@@ -372,8 +479,10 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 	 * Use the address following the image as target address for the
 	 * device tree.
 	 */
-	image_info.load_addr = spl_image->load_addr + spl_image->size;
-
+#ifndef CVI_SPL_FDT_SIZE
+#define CVI_SPL_FDT_SIZE 0x100000
+#endif
+	image_info.load_addr = (uintptr_t)malloc(CVI_SPL_FDT_SIZE);
 	/* Figure out which device tree the board wants to use */
 	node = spl_fit_get_image_node(ctx, FIT_FDT_PROP, index++);
 	if (node < 0) {
@@ -458,6 +567,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image,
 	if (ret < 0)
 		return ret;
 
+	spl_image_setup_libfdt(image_info, ctx);
 	return ret;
 }
 
@@ -529,6 +639,8 @@ static void *spl_get_fit_load_buffer(size_t size)
 {
 	void *buf;
 
+	return (void *)UIMAG_ADDR;
+
 	buf = malloc(size);
 	if (!buf) {
 		pr_err("Could not get FIT buffer of %lu bytes\n", (ulong)size);
@@ -718,7 +830,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
 		      __func__, node);
 		return -1;
 	}
-
+	// Save decompression start time
+	board_save_time_record(TIME_RECORDS_FIELD_DECOMPRESS_KERNEL_START);
 	/* Load the image and set up the spl_image structure */
 	ret = spl_load_fit_image(info, sector, &ctx, node, spl_image);
 	if (ret)

u-boot-2021.10/common/spl/spl_nor.c

@@ -7,12 +7,66 @@
 #include <image.h>
 #include <log.h>
 #include <spl.h>
+#include "mmio.h"
+
+#define REG_BASE                        0x10000000
+#define REG_SPI_CTRL                    0x00
+#define REG_SPI_CE_CTRL                 0x04
+#define REG_SPI_DLY_CTRL                0x08
+#define REG_SPI_DMMR                    0x0C
+#define REG_SPI_TRAN_CSR                0x10
+#define REG_SPI_TRAN_NUM                0x14
+#define REG_SPI_FIFO_PORT               0x18
+#define REG_SPI_FIFO_PT                 0x20
+#define REG_SPI_INT_STS                 0x28
+#define REG_SPI_INT_EN                  0x2C
+#define REG_SPI_OPT                     0x30
+
+#define BIT_SPI_CTRL_SCK_DIV_MASK       0x7FF
+#define BIT_SPI_DLY_CTRL_CET            (3 << 8)
+#define BIT_SPI_DLY_CTRL_NEG_SAMPLE     BIT(14)
+
+#ifndef CONFIG_SYS_OS_BASE
+#define CONFIG_SYS_OS_BASE		0x300000
+#endif
+
+typedef enum {
+	Uninitialized,
+	Initialized
+} spinor_status_e;
+static spinor_status_e spinor_status = Uninitialized;
+
+static void cvi_spi_nor_init(void)
+{
+	uint32_t reg;
+
+	mmio_write_32(REG_BASE + REG_SPI_DMMR, 0);
+	reg = mmio_read_32(REG_BASE + REG_SPI_CTRL);
+	reg &= ~BIT_SPI_CTRL_SCK_DIV_MASK;
+	/* set clock to 75M */
+	reg |= 1;
+	mmio_write_32(REG_BASE + REG_SPI_CTRL, reg);
+	/* negative sample */
+	mmio_write_16(REG_BASE + REG_SPI_DLY_CTRL, BIT_SPI_DLY_CTRL_CET | BIT_SPI_DLY_CTRL_NEG_SAMPLE);
+	mmio_write_32(REG_SPI_CE_CTRL, 0);
+
+	reg = 0x003BA9;
+	reg &= ~(0xf << 16);
+	reg |= (6 << 16);
+	mmio_write_32(REG_BASE + REG_SPI_TRAN_CSR, reg);
+
+	mmio_write_32(REG_BASE + REG_SPI_DMMR, 1);
+
+}
 
 static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
 			       ulong count, void *buf)
 {
 	debug("%s: sector %lx, count %lx, buf %p\n",
 	      __func__, sector, count, buf);
+	if (spinor_status != Initialized)
+		cvi_spi_nor_init();
+
 	memcpy(buf, (void *)sector, count);
 
 	return count;
@@ -20,7 +74,7 @@ static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector,
 
 unsigned long __weak spl_nor_get_uboot_base(void)
 {
-	return CONFIG_SYS_UBOOT_BASE;
+	return 0;//CONFIG_SYS_UBOOT_BASE;	// not use
 }
 
 static int spl_nor_load_image(struct spl_image_info *spl_image,
@@ -41,7 +95,11 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 		 * Load Linux from its location in NOR flash to its defined
 		 * location in SDRAM
 		 */
-		header = (const struct image_header *)CONFIG_SYS_OS_BASE;
+		if (spinor_status != Initialized) {
+			cvi_spi_nor_init();
+			spinor_status = Initialized;
+		}
+		header = (const struct image_header *)(REG_BASE + SPL_BOOT_PART_OFFSET);
 #ifdef CONFIG_SPL_LOAD_FIT
 		if (image_get_magic(header) == FDT_MAGIC) {
 			int ret;
@@ -51,7 +109,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 			load.read = spl_nor_load_read;
 
 			ret = spl_load_simple_fit(spl_image, &load,
-						  CONFIG_SYS_OS_BASE,
+						  (REG_BASE + SPL_BOOT_PART_OFFSET),
 						  (void *)header);
 
 #if defined CONFIG_SYS_SPL_ARGS_ADDR && defined CONFIG_CMD_SPL_NOR_OFS
@@ -61,6 +119,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 #endif
 			return ret;
 		}
+		printf("Not Found FIT\n");
 #endif
 		if (image_get_os(header) == IH_OS_LINUX) {
 			/* happy - was a Linux */
@@ -71,7 +130,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image,
 				return ret;
 
 			memcpy((void *)spl_image->load_addr,
-			       (void *)(CONFIG_SYS_OS_BASE +
+			       (void *)((REG_BASE + SPL_BOOT_PART_OFFSET) +
 					sizeof(struct image_header)),
 			       spl_image->size);
 #ifdef CONFIG_SYS_FDT_BASE

u-boot-2021.10/drivers/video/cvitek/cvi_mipi.c

@@ -94,8 +94,7 @@ int mipi_tx_set_combo_dev_cfg(const struct combo_dev_cfg_s *dev_cfg)
 	struct combo_dev_cfg_s dev_cfg_t = *dev_cfg;
 	struct disp_ctrl_gpios ctrl_gpios;
 
-	sclr_disp_set_intf(SCLR_VO_INTF_MIPI);
-
+	dphy_dsi_disable_lanes();
 	for (i = 0; i < LANE_MAX_NUM; i++) {
 		if ((dev_cfg_t.lane_id[i] < 0) || (dev_cfg_t.lane_id[i] >= MIPI_TX_LANE_MAX)) {
 			data_en[i] = false;
@@ -142,6 +141,7 @@ int mipi_tx_set_combo_dev_cfg(const struct combo_dev_cfg_s *dev_cfg)
 	preamble_on = (dev_cfg_t.pixel_clk * bits / lane_num) > 1500000;
 	dphy_dsi_lane_en(true, data_en, preamble_on);
 	dphy_dsi_set_pll(dev_cfg_t.pixel_clk, lane_num, bits);
+	sclr_disp_set_intf(SCLR_VO_INTF_MIPI);
 	sclr_dsi_config(lane_num, dsi_fmt, dev_cfg_t.sync_info.vid_hline_pixels);
 	sclr_disp_set_timing(&timing);
 	sclr_disp_tgen_enable(true);

u-boot-2021.10/drivers/video/cvitek/dsi_phy.c

@@ -42,6 +42,13 @@ void dphy_dsi_lane_en(bool clk_en, bool *data_en, bool preamble_en)
 	_reg_write_mask(reg_base + REG_DSI_PHY_EN, 0x3f, val);
 }
 
+int dphy_dsi_disable_lanes(void)
+{
+	_reg_write_mask(reg_base + REG_DSI_PHY_EN, 0x3f, 0);
+	_reg_write_mask(reg_base + REG_DSI_PHY_LANE_SEL, 0xfffff, 0xfffff);
+	return 0;
+}
+
 /**
  * dphy_dsi_set_lane - dsi-lanes control.
  *                     setup before dphy_dsi_lane_en().
@@ -82,8 +89,23 @@ void dphy_lvds_enable(bool en)
  */
 void dphy_init(enum sclr_vo_intf intf)
 {
+	int lptrx = 0, lptx_rx = 0, hstx = 0, i;
+
+	for (i = 0; i < DSI_LANE_MAX; ++i) {
+		if (((_reg_read(reg_base + REG_DSI_PHY_LANE_SEL) >> i * 4) & 0x0F) > 4) {
+			lptrx |= ((1 << i) | (1 << (8 + i)));
+			lptx_rx  |= ((1 << i) | (1 << (16 + i)));
+			hstx  |= ((1 << i) | (1 << (8 + i)) | (1 << (16 + i)) | (1 << (24 + i)));
+		}
+	}
+
 	_reg_write(reg_base + REG_DSI_PHY_PD, (intf == SCLR_VO_INTF_MIPI || intf == SCLR_VO_INTF_LVDS
-		) ? 0x0 : 0x1f1f);
+		) ? lptrx : 0x1f1f);
+	_reg_write(reg_base + REG_DSI_PHY_LPTX_OV, lptx_rx);
+	_reg_write(reg_base + REG_DSI_PHY_PD_EN_TX, lptrx);
+	_reg_write(reg_base + REG_DSI_PHY_PD_TXDRV, hstx);
+	_reg_write(reg_base + REG_DSI_PHY_GPO, lptrx);
+	_reg_write(reg_base + REG_DSI_PHY_GPI, lptrx);
 	_reg_write(reg_base + REG_DSI_PHY_ESC_INIT, 0x100);
 	_reg_write(reg_base + REG_DSI_PHY_ESC_WAKE, 0x100);
 
@@ -120,20 +142,27 @@ void _cal_pll_reg(u32 clkkHz, u32 VCOR_10000, u32 *reg_txpll, u32 *reg_set, u32
 	u8 dig_dig = (u8)ilog2(gain);
 	u8 reg_divout_sel = min((u8)3, dig_dig);
 	u8 reg_div_sel = dig_dig - reg_divout_sel;
-	u8 loop_gain = (((VCOC_1000 / 133000) + 7) >> 3) << 3;
+	u32 loop_gainx1000 = VCOC_1000 / 133;
 	bool bt_div = reg_disp_div_sel > 0x7f;
-	u32 loop_c = 8 * ((VCOC_1000 / 133 / 8) + 500) / 1000;
+	u32 loop_c = 8 * ((loop_gainx1000 / 8) / 1000);
 	u8 div_loop = loop_c > 32 ? 3 : loop_c / 8;
+	u8 loop_gain1 = div_loop * 8;
+
+	*reg_set = ((u64)(factor * loop_gain1) << 26) / VCOC_1000;
 
-	*reg_set = ((u64)(factor * loop_gain) << 26) / VCOC_1000;
+	if (bt_div) {
+		vip_sys_reg_write_mask(VIP_SYS_VIP_CLK_CTRL0, 0x10, 0);
+		reg_disp_div_sel >>= 1;
+	} else
+		vip_sys_reg_write_mask(VIP_SYS_VIP_CLK_CTRL0, 0x10, 0x10);
 
 	_reg_write_mask(reg_base + REG_DSI_PHY_TXPLL, 0x300000, div_loop << 20);
 
 	*reg_txpll = (reg_div_sel << 10) | (reg_divout_sel << 8) | reg_disp_div_sel;
 #if 0
 	pr_info("clkkHz(%d) VCOR_10000(%d) gain(%d)\n", clkkHz, VCOR_10000, gain);
-	pr_info("VCOC_1000(%d) dig_dig(%d) loop_gain(%d)\n", VCOC_1000, dig_dig, loop_gain);
-	pr_info("loop_c(%d) div_loop(%d) loop_gain1(%d)\n", loop_c, div_loop, div_loop * 2);
+	pr_info("VCOC_1000(%d) dig_dig(%d) loop_gain(%d)\n", VCOC_1000, dig_dig, loop_gainx1000);
+	pr_info("loop_c(%d) div_loop(%d) loop_gain1(%d)\n", loop_c, div_loop, loop_gain1);
 	pr_info("regs: disp_div_sel(%d), divout_sel(%d), div_sel(%d), set(%#x)\n",
 		reg_disp_div_sel, reg_divout_sel, reg_div_sel, *reg_set);
 #endif
@@ -145,10 +174,13 @@ void dphy_lvds_set_pll(u32 clkkHz, u8 link)
 	u32 VCOR_10000 = clkkHz * 70 / link;
 	u32 reg_txpll, reg_set;
 
-	_cal_pll_reg(clkkHz, VCOR_10000, &reg_txpll, &reg_set, 1200000);
+	_cal_pll_reg(clkkHz, VCOR_10000, &reg_txpll, &reg_set, 900000);
 
 	_reg_write_mask(reg_base + REG_DSI_PHY_TXPLL, 0x7ff, reg_txpll);
 	_reg_write(reg_base + REG_DSI_PHY_REG_SET, reg_set);
+	// update
+	_reg_write_mask(reg_base + REG_DSI_PHY_REG_8C, BIT(0), 0);
+	_reg_write_mask(reg_base + REG_DSI_PHY_REG_8C, BIT(0), 1);
 }
 
 void dphy_dsi_set_pll(u32 clkkHz, u8 lane, u8 bits)

u-boot-2021.10/drivers/video/cvitek/dsi_phy.h

@@ -20,6 +20,7 @@ enum lane_id {
 void dphy_set_base_addr(void *base);
 void dphy_dsi_lane_en(bool clk_en, bool *data_en, bool preamble_en);
 int dphy_dsi_set_lane(u8 lane_num, enum lane_id lane, bool pn_swap, bool clk_phase_shift);
+int dphy_dsi_disable_lanes(void);
 void dphy_init(enum sclr_vo_intf intf);
 void dphy_dsi_set_pll(u32 clkkHz, u8 lane, u8 bits);
 void dphy_lvds_enable(bool en);

u-boot-2021.10/drivers/video/cvitek/scaler_reg.h

@@ -134,6 +134,8 @@
 #define REG_DSI_PHY_DATA_OV        (REG_DSI_WRAP_BASE + 0x44)
 #define REG_DSI_PHY_LPTX_OV        (REG_DSI_WRAP_BASE + 0x4C)
 #define REG_DSI_PHY_LPRX_OV        (REG_DSI_WRAP_BASE + 0x4C)
+#define REG_DSI_PHY_PD_TXDRV       (REG_DSI_WRAP_BASE + 0x50)
+#define REG_DSI_PHY_PD_EN_TX       (REG_DSI_WRAP_BASE + 0x54)
 #define REG_DSI_PHY_PD             (REG_DSI_WRAP_BASE + 0x64)
 #define REG_DSI_PHY_TXPLL          (REG_DSI_WRAP_BASE + 0x6C)
 #define REG_DSI_PHY_REG_74         (REG_DSI_WRAP_BASE + 0x74)
@@ -143,5 +145,7 @@
 #define REG_DSI_PHY_LANE_PN_SWAP   (REG_DSI_WRAP_BASE + 0xA0)
 #define REG_DSI_PHY_LVDS_EN        (REG_DSI_WRAP_BASE + 0xB4)
 #define REG_DSI_PHY_EXT_GPIO       (REG_DSI_WRAP_BASE + 0xC0)
+#define REG_DSI_PHY_GPO            (REG_DSI_WRAP_BASE + 0xC4)
+#define REG_DSI_PHY_GPI            (REG_DSI_WRAP_BASE + 0xC8)
 
 #endif  // _CVI_SCL_REG_H_

u-boot-2021.10/include/configs/cv180x-asic.h

@@ -222,11 +222,16 @@
 
 	/* config loglevel */
 	#ifdef RELEASE
-		#define OTHERBOOTARGS   "othbootargs=earlycon=sbi release loglevel=0 riscv.fwsz=0x80000\0"
+		#define CONSOLE_LOGLEVEL   " loglevel=0"
+		#define EARLYCON_RELEASE   " release "
 	#else
-		#define OTHERBOOTARGS   "othbootargs=earlycon=sbi loglevel=9 riscv.fwsz=0x80000\0"
+		#define CONSOLE_LOGLEVEL   " loglevel=9"
+		#define EARLYCON_RELEASE   " "
 	#endif
 
+	#define OTHERBOOTARGS   "earlycon=sbi riscv.fwsz="  __stringify(CVIMMAP_OPENSBI_SIZE) \
+		EARLYCON_RELEASE CONSOLE_LOGLEVEL
+
 	/* config mtdids */
 	#ifdef CONFIG_NAND_SUPPORT
 		#define MTDIDS_DEFAULT "nand0=cvsnfc"
@@ -246,7 +251,7 @@
 		"mtdids=" MTDIDS_DEFAULT "\0" \
 		"root=" ROOTARGS "\0" \
 		"sdboot=" SD_BOOTM_COMMAND "\0" \
-		OTHERBOOTARGS \
+		"othbootargs=" OTHERBOOTARGS "\0"\
 		PARTS_OFFSET
 
 /********************************************************************************/
@@ -279,7 +284,7 @@
 		#define SHOWLOGOCMD
 	#endif
 
-	#define SET_BOOTARGS "setenv bootargs ${root} ${mtdparts} " \
+	#define SET_BOOTARGS "setenv bootargs ${reserved_mem} ${root} ${mtdparts} " \
 					"console=$consoledev,$baudrate $othbootargs;"
 
 	#define SD_BOOTM_COMMAND \
@@ -325,4 +330,9 @@
 
 #endif /* CONFIG_USE_DEFAULT_ENV */
 
+#define CVI_SPL_BOOTAGRS \
+	PARTS " "  \
+	ROOTARGS " " \
+	"console=ttyS0,115200 " \
+	OTHERBOOTARGS "\0"
 #endif /* __CV181X_ASIC_H__ */

u-boot-2021.10/include/configs/cv181x-asic.h

@@ -222,11 +222,16 @@
 
 	/* config loglevel */
 	#ifdef RELEASE
-		#define OTHERBOOTARGS   "othbootargs=earlycon=sbi release loglevel=0 riscv.fwsz=0x80000\0"
+		#define CONSOLE_LOGLEVEL   " loglevel=0"
+		#define EARLYCON_RELEASE   " release "
 	#else
-		#define OTHERBOOTARGS   "othbootargs=earlycon=sbi loglevel=9 riscv.fwsz=0x80000\0"
+		#define CONSOLE_LOGLEVEL   " loglevel=9"
+		#define EARLYCON_RELEASE   " "
 	#endif
 
+	#define OTHERBOOTARGS   "earlycon=sbi riscv.fwsz="  __stringify(CVIMMAP_OPENSBI_SIZE) " " \
+		EARLYCON_RELEASE CONSOLE_LOGLEVEL
+
 	/* config mtdids */
 	#ifdef CONFIG_NAND_SUPPORT
 		#define MTDIDS_DEFAULT "nand0=cvsnfc"
@@ -246,7 +251,7 @@
 		"mtdids=" MTDIDS_DEFAULT "\0" \
 		"root=" ROOTARGS "\0" \
 		"sdboot=" SD_BOOTM_COMMAND "\0" \
-		OTHERBOOTARGS \
+		"othbootargs=" OTHERBOOTARGS "\0" \
 		PARTS_OFFSET
 
 /********************************************************************************/
@@ -279,7 +284,7 @@
 		#define SHOWLOGOCMD
 	#endif
 
-	#define SET_BOOTARGS "setenv bootargs ${root} ${mtdparts} " \
+	#define SET_BOOTARGS "setenv bootargs ${reserved_mem} ${root} ${mtdparts} " \
 					"console=$consoledev,$baudrate $othbootargs;"
 
 	#define SD_BOOTM_COMMAND \
@@ -321,4 +326,9 @@
 
 #endif /* CONFIG_USE_DEFAULT_ENV */
 
+#define CVI_SPL_BOOTAGRS \
+	PARTS " "  \
+	ROOTARGS " " \
+	"console=ttyS0,115200 " \
+	OTHERBOOTARGS "\0"
 #endif /* __CV181X_ASIC_H__ */

u-boot-2021.10/include/cvitek/cvi_panels/cvi_panels.h

@@ -113,6 +113,15 @@ static struct panel_desc_s panel_desc = {
 	.dsi_init_cmds = dsi_init_cmds_st7701_480x800,
 	.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7701_480x800)
 };
+#elif defined(MIPI_PANEL_ST7785M)
+#include "dsi_st7785m.h"
+static struct panel_desc_s panel_desc = {
+	.panel_name = "ST77825M-240x320",
+	.dev_cfg = &dev_cfg_st7785m_240x320,
+	.hs_timing_cfg = &hs_timing_cfg_st7785m_240x320,
+	.dsi_init_cmds = dsi_init_cmds_st7785m_240x320,
+	.dsi_init_cmds_size = ARRAY_SIZE(dsi_init_cmds_st7785m_240x320)
+};
 #elif defined(I80_PANEL_ST7789V)
 #include "i80_st7789v.h"
 static struct panel_desc_s panel_desc = {

u-boot-2021.10/include/cvitek/cvi_panels/dsi_st7785m.h

+#ifndef _MIPI_TX_PARAM_ST7785M_H_
+#define _MIPI_TX_PARAM_ST7785M_H_
+
+#include <cvi_mipi.h>
+
+#define ST7785M_HACT	240
+#define ST7785M_HSA		10
+#define ST7785M_HBP		80
+#define ST7785M_HFP		80
+
+#define ST7785M_VACT	320
+#define ST7785M_VSA		10
+#define ST7785M_VBP		20
+#define ST7785M_VFP		20
+
+#define PIXEL_CLK(x) ((x##_VACT + x##_VSA + x##_VBP + x##_VFP) \
+	* (x##_HACT + x##_HSA + x##_HBP + x##_HFP) * 60 / 1000)
+
+struct combo_dev_cfg_s dev_cfg_st7785m_240x320 = {
+	.devno = 0,
+	.lane_id = {MIPI_TX_LANE_0, MIPI_TX_LANE_CLK, -1, -1, -1},
+	.lane_pn_swap = {true, true, true, true, true},
+	.output_mode = OUTPUT_MODE_DSI_VIDEO,
+	.video_mode = BURST_MODE,
+	.output_format = OUT_FORMAT_RGB_24_BIT,
+	.sync_info = {
+		.vid_hsa_pixels = ST7785M_HSA,
+		.vid_hbp_pixels = ST7785M_HBP,
+		.vid_hfp_pixels = ST7785M_HFP,
+		.vid_hline_pixels = ST7785M_HACT,
+		.vid_vsa_lines = ST7785M_VSA,
+		.vid_vbp_lines = ST7785M_VBP,
+		.vid_vfp_lines = ST7785M_VFP,
+		.vid_active_lines = ST7785M_VACT,
+		.vid_vsa_pos_polarity = true,
+		.vid_hsa_pos_polarity = true,
+	},
+	.pixel_clk = PIXEL_CLK(ST7785M),
+};
+
+const struct hs_settle_s hs_timing_cfg_st7785m_240x320 = { .prepare = 6, .zero = 32, .trail = 1 };
+
+static u8 data_st7785m_0[] = { 0x11 };
+static u8 data_st7785m_1[] = { 0x36, 0x00, 0x00 };
+static u8 data_st7785m_2[] = { 0x3a, 0x00, 0x66 };
+static u8 data_st7785m_3[] = { 0xb0, 0x00, 0x10 };
+static u8 data_st7785m_4[] = { 0xb2, 0x00, 0x0c, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x33, 0x00, 0x33 };
+static u8 data_st7785m_5[] = { 0xb7, 0x00, 0x51 };
+static u8 data_st7785m_6[] = { 0xbb, 0x00, 0x1e };
+static u8 data_st7785m_7[] = { 0xc0, 0x00, 0x2c };
+static u8 data_st7785m_8[] = { 0xc2, 0x00, 0x01 };
+static u8 data_st7785m_9[] = { 0xc3, 0x00, 0x13 };
+static u8 data_st7785m_10[] = { 0xc6, 0x00, 0x0f };
+static u8 data_st7785m_11[] = { 0xd0, 0x00, 0xa7 };
+static u8 data_st7785m_12[] = { 0xd0, 0x00, 0xa4, 0x00, 0xa1 };
+static u8 data_st7785m_13[] = { 0xe0, 0x00, 0xF0, 0x00, 0x0C, 0x00,
+									0x14, 0x00, 0x0C, 0x00, 0x0C, 0x00,
+									0x09, 0x00, 0x3B, 0x00, 0x44, 0x00,
+									0x52, 0x00, 0x3A, 0x00, 0x14, 0x00,
+									0x15, 0x00, 0x35, 0x00, 0x3B };
+static u8 data_st7785m_14[] = { 0xe1, 0x00, 0xF0, 0x00, 0x0F, 0x00,
+									0x16, 0x00, 0x09, 0x00, 0x08, 0x00,
+									0x23, 0x00, 0x3B, 0x00, 0x33, 0x00,
+									0x52, 0x00, 0x25, 0x00, 0x0F, 0x00,
+									0x11, 0x00, 0x33, 0x00, 0x39 };
+
+static u8 data_st7785m_15[] = { 0x21 };
+static u8 data_st7785m_16[] = { 0x11 };
+static u8 data_st7785m_17[] = { 0x29 };
+
+const struct dsc_instr dsi_init_cmds_st7785m_240x320[] = {
+	{.delay = 120, .data_type = 0x05, .size = 1, .data = data_st7785m_0 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_1 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_2 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_3 },
+	{.delay = 10, .data_type = 0x29, .size = 11, .data = data_st7785m_4 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_5 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_6 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_7 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_8 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_9 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_10 },
+	{.delay = 10, .data_type = 0x29, .size = 3, .data = data_st7785m_11 },
+	{.delay = 10, .data_type = 0x29, .size = 5, .data = data_st7785m_12 },
+	{.delay = 10, .data_type = 0x29, .size = 29, .data = data_st7785m_13 },
+	{.delay = 10, .data_type = 0x29, .size = 29, .data = data_st7785m_14 },
+	{.delay = 10, .data_type = 0x05, .size = 1, .data = data_st7785m_15 },
+	{.delay = 120, .data_type = 0x05, .size = 1, .data = data_st7785m_16 },
+	{.delay = 20, .data_type = 0x05, .size = 1, .data = data_st7785m_17 },
+
+};
+
+#else
+#error "MIPI_TX_PARAM multi-delcaration!!"
+#endif // _MIPI_TX_PARAM_ST7785M_H_

u-boot-2021.10/lib/lzma/LzmaTools.c

@@ -91,8 +91,8 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
         }
     }
 
-    debug("LZMA: Uncompresed size............ 0x%zx\n", outSizeFull);
-    debug("LZMA: Compresed size.............. 0x%zx\n", compressedSize);
+	debug("LZMA: Uncompresed size............ 0x%lx\n", outSizeFull);
+	debug("LZMA: Compresed size.............. 0x%lx\n", compressedSize);
 
     g_Alloc.Alloc = SzAlloc;
     g_Alloc.Free = SzFree;
@@ -112,7 +112,7 @@ int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
         inStream, LZMA_PROPS_SIZE, LZMA_FINISH_END, &state, &g_Alloc);
     *uncompressedSize = outProcessed;
 
-    debug("LZMA: Uncompressed ............... 0x%zx\n", outProcessed);
+	debug("LZMA: Uncompressed ............... 0x%lx\n", outProcessed);
 
     if (res != SZ_OK)  {
         return res;

u-boot-2021.10/lib/time.c

@@ -24,9 +24,12 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !CONFIG_IS_ENABLED(TIMER) && CONFIG_SPL
+#define CONFIG_SYS_TIMER_RATE 25000000	// 25M
+#endif
 #ifdef CONFIG_SYS_TIMER_RATE
 /* Returns tick rate in ticks per second */
-ulong notrace get_tbclk(void)
+__weak ulong notrace get_tbclk(void)
 {
 	return CONFIG_SYS_TIMER_RATE;
 }

u-boot-2021.10/scripts/Makefile.spl

@@ -183,8 +183,8 @@ LDPPFLAGS += \
 
 # Turn various CONFIG symbols into IMAGE symbols for easy reuse of
 # the scripts between SPL and TPL.
-ifneq ($(CONFIG_$(SPL_TPL_)MAX_SIZE),)
-LDPPFLAGS += -DIMAGE_MAX_SIZE=$(CONFIG_$(SPL_TPL_)MAX_SIZE)
+ifneq ($(CONFIG_$(SPL_TPL_)SIZE_LIMIT),)
+LDPPFLAGS += -DIMAGE_MAX_SIZE=$(CONFIG_$(SPL_TPL_)SIZE_LIMIT)
 endif
 ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
 LDPPFLAGS += -DIMAGE_TEXT_BASE=$(CONFIG_$(SPL_TPL_)TEXT_BASE)

u-boot-2021.10/tools/env/Makefile

@@ -7,7 +7,6 @@
 # built with cross tools. Although it may look weird, we only replace "HOSTCC"
 # with "CC" here for the maximum code reuse of scripts/Makefile.host.
 override HOSTCC = $(CC)
-
 # Compile for a hosted environment on the target
 HOST_EXTRACFLAGS  = -I$(srctree)/tools \
 		$(patsubst -I%,-idirafter%, $(filter -I%, $(UBOOTINCLUDE))) \
@@ -33,5 +32,7 @@ quiet_cmd_crosstools_strip = STRIP   $^
 
 $(obj)/.strip: $(obj)/fw_printenv
 	$(call cmd,crosstools_strip)
+	rm -rf $(obj)/fw_setenv
+	ln -s fw_printenv $(obj)/fw_setenv
 
 always += .strip

u-boot-2021.10/tools/spl_size_limit.c

@@ -4,7 +4,7 @@
  *
  * This tool helps to return the size available for SPL image during build
  */
-
+#include <config.h>
 #include <generated/autoconf.h>
 #include <generated/generic-asm-offsets.h>