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duo-buildroot-sdk
Commit 1f388afc authored by forum_service's avatar forum_service Committed by carbon
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u-boot: version release v4.1.0.3 

fa813205bd Merge "[eth] change rxterm and vcm to link DianXin router" into v4.1.0
956d3a3198 [eth] change rxterm and vcm to link DianXin router
9e6d7e0dd8 [audio][uboot] add play

Change-Id: I6a23283cc4033f4032f0161d4ba5b9339e8f9952
parent b5490999
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Showing with 2365 additions and 18 deletions
u-boot-2021.10/cmd/Kconfig
View file @ 1f388afc
......@@ -2418,6 +2418,12 @@ config CMD_CVI_JPEG
and decode jpg file to yuv format to the
destination address
config CMD_CVISOUND
bool "CVI sound"
help
Support for the audio play
config CMD_CVI_UPDATE
bool "cvitek update command"
default y
......
u-boot-2021.10/cmd/Makefile
View file @ 1f388afc
......@@ -206,6 +206,7 @@ obj-$(CONFIG_CMD_AVB) += avb.o
obj-$(CONFIG_CMD_SCP03) += scp03.o
obj-y += efuse.o
obj-$(CONFIG_CMD_CVISOUND) += cvisound.o
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/
......
u-boot-2021.10/cmd/cvisound.c 0 → 100644
View file @ 1f388afc
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2023 bitmain, Inc
*
*/
#include <common.h>
#include <command.h>
#include <dm.h>
#include <sound.h>
#include <mapmem.h>
#include <dm/uclass.h>
#include <dm/uclass.h>
#include "../drivers/cvi_sound/cvi-src.h"
static int do_play(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int ret = 0;
struct udevice *dev;
const struct sound_ops *ops;
printf("enter cviplay\n");
ret = uclass_get_device_by_driver(UCLASS_SOUND, DM_DRIVER_GET(cvitekub_sound), &dev);
if (ret) {
printf("[error][%s]no cvitekub_sound device ret:%d\n", __func__, ret);
return -1;
}
ops = dev->driver->ops;
if (!ops->setup || !ops->play || !ops->stop_play) {
printf("[error][%s]setup:%p, play:%p, stop_play:%p\n",
__func__, ops->setup, ops->play, ops->stop_play);
return -1;
}
ops->setup(dev);
ret = ops->play(dev, src_tx_data, SRC_BUFF_SIZE);
//printf("UPDATE_ADDR:%ld\n", (uintptr_t)UPDATE_ADDR);
//ret = ops->play(dev, (void *)(uintptr_t)UPDATE_ADDR, 726904);
if (ret) {
printf("[error][%s]play error:%d\n", __func__, ret);
return -1;
}
ops->stop_play(dev);
return 0;
}
U_BOOT_CMD(cviplay, 1, 1, do_play,
"perform cviplay",
"play sound\n"
);
u-boot-2021.10/drivers/Kconfig
View file @ 1f388afc
......@@ -109,6 +109,7 @@ source "drivers/serial/Kconfig"
source "drivers/smem/Kconfig"
source "drivers/sound/Kconfig"
source "drivers/cvi_sound/Kconfig"
source "drivers/soc/Kconfig"
......
u-boot-2021.10/drivers/Makefile
View file @ 1f388afc
......@@ -72,9 +72,10 @@ ifdef CONFIG_TPL_BUILD
obj-$(CONFIG_TPL_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
endif
obj-y += cvi_sound/
ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-y += adc/
......
u-boot-2021.10/drivers/cvi_sound/Kconfig 0 → 100644
View file @ 1f388afc
menu "Cvitek Sound support"
config CVI_SOUND_DRIVERS
bool "Enable cvitek sound support"
help
Support making sounds through an audio codec. This is normally a
beep at a chosen frequency for a selected length of time. However
the drivers support playing arbitrary sound samples using a
PCM interface.
endmenu
u-boot-2021.10/drivers/cvi_sound/Makefile 0 → 100644
View file @ 1f388afc
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2023 Bitmain
#
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-sound.o
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-sound-uclass.o
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-dac-uclass.o
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-dac.o
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-i2s-uclass.o
obj-$(CONFIG_CVI_SOUND_DRIVERS) += cvi-i2s.o
u-boot-2021.10/drivers/cvi_sound/cvi-dac-uclass.c 0 → 100644
View file @ 1f388afc
#define LOG_CATEGORY UCLASS_AUDIO_CODEC
#include <common.h>
#include <dm.h>
#include "cvi-dac.h"
#include <audio_codec.h>
#include <dm/uclass.h>
int audio_codec_set_params(struct udevice *dev, int interface, int rate,
int mclk_freq, int bits_per_sample, uint channels)
{
struct audio_codec_ops *ops = audio_codec_get_ops(dev);
if (!ops->set_params)
return -ENOSYS;
return ops->set_params(dev, interface, rate, mclk_freq, bits_per_sample,
channels);
}
int audio_codec_close(struct udevice *dev)
{
struct audio_codec_ops *ops = audio_codec_get_ops(dev);
if (!ops->codec_close)
return -ENOSYS;
return ops->codec_close(dev);
}
UCLASS_DRIVER(audio_codec) = {
.id = UCLASS_AUDIO_CODEC,
.name = "audio-codec",
};
u-boot-2021.10/drivers/cvi_sound/cvi-dac.c 0 → 100644
View file @ 1f388afc
#include <dm/device.h>
#include "cvi-dac.h"
#include <audio_codec.h>
#include <time.h>
struct cvitekdac_priv {
//enum maxim_codec_type devtype;
unsigned int sysclk;
unsigned int rate;
unsigned int fmt;
struct udevice *dev;
};
static struct cv182xdac g_dac;
static struct cv182xdac *dac;
static int cv182xdac_hw_params(struct cv182xdac *dac, u32 chan_nr, u32 rate)
{
u32 ctrl1 = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL1) & ~AUDIO_PHY_REG_TXDAC_CIC_OPT_MASK;
u32 tick = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE0) & ~AUDIO_PHY_REG_TXDAC_INIT_DLY_CNT_MASK;
u32 ana2 = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
switch (chan_nr) {
case 1:
ana2 &= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFF; /* turn R-channel on */
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, ana2);
break;
default:
ana2 &= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFF; /* turn R-channel on */
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, ana2);
break;
}
if (rate >= 8000 && rate <= 48000) {
debug("%s, set rate to %d\n", __func__, rate);
switch (rate) {
case 8000:
ctrl1 |= TXDAC_CIC_DS_512;
tick |= 0x21;
break;
case 11025:
ctrl1 |= TXDAC_CIC_DS_256;
tick |= 0x17;
break;
case 16000:
ctrl1 |= TXDAC_CIC_DS_256;
tick |= 0x21;
break;
case 22050:
ctrl1 |= TXDAC_CIC_DS_128;
tick |= 0x17;
break;
case 32000:
ctrl1 |= TXDAC_CIC_DS_128;
tick |= 0x21;
break;
case 44100:
ctrl1 &= TXDAC_CIC_DS_64;
tick |= 0x17;
break;
case 48000:
ctrl1 &= TXDAC_CIC_DS_64;
tick |= 0x19;
break;
default:
ctrl1 |= TXDAC_CIC_DS_256;
tick |= 0x21;
debug("%s, set sample rate with default 16KHz\n", __func__);
break;
}
} else {
printf("%s, unsupported sample rate\n", __func__);
return 0;
}
debug("%s, ctrl1=0x%x\n", __func__, ctrl1);
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL1, ctrl1);
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE0, tick);
return 0;
}
static void cv182xdac_on(struct cv182xdac *dac)
{
u32 val = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
debug("%s, before ctrl0_reg val=0x%08x\n", __func__, val);
if ((val & AUDIO_PHY_REG_TXDAC_EN_ON) | (val & AUDIO_PHY_REG_I2S_RX_EN_ON))
printf("DAC already switched ON!!, val=0x%08x\n", val);
val |= AUDIO_PHY_REG_TXDAC_EN_ON | AUDIO_PHY_REG_I2S_RX_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, val);
debug("%s, after ctrl0_reg val=0x%08x\n",
__func__, dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0));
}
static void cv182xdac_off(struct cv182xdac *dac)
{
u32 val = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
debug("%s, before ctrl_reg val=0x%08x\n",
__func__, dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0));
val &= AUDIO_PHY_REG_TXDAC_EN_OFF & AUDIO_PHY_REG_I2S_RX_EN_OFF;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, val);
debug("%s, after ctrl_reg val=0x%08x\n",
__func__, dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0));
}
static void cv182xdac_shutdown(void)
{
cv182x_reset_dac();
cv182xdac_off(dac);
printf("%s\n", __func__);
}
int cv182xdac_ioctl(u32 cmd, struct cvi_vol_ctrl vol, u32 val)
{
u32 temp = 0;
dac->dac_base = (volatile u32 *)(0x0300A000);
switch (cmd) {
case ACODEC_SOFT_RESET_CTRL:
cv182x_reset_dac();
break;
case ACODEC_SET_OUTPUT_VOL:
debug("dac: ACODEC_SET_OUTPUT_VOL with val=%d\n", val);
if ((val < 0) | (val > 32))
printf("Only support range 0 [mute] ~ 32 [maximum]\n");
else {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
& ~(AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK | AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK);
temp |= DAC_VOL_L(val) | DAC_VOL_R(val);
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1, temp);
}
break;
case ACODEC_GET_OUTPUT_VOL:
debug("dac: ACODEC_GET_OUTPUT_VOL\n");
temp = ((dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
& AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK) + 1) / CV182x_DAC_VOL_STEP;
debug("dac: return val=%d\n", temp);
//_/ if (copy_to_user(argp, &temp, sizeof(temp)))
//_/ printf("dac, failed to return output vol\n");
break;
case ACODEC_SET_I2S1_FS:
debug("dac: ACODEC_SET_I2S1_FS is not support\n");
break;
case ACODEC_SET_DACL_VOL:
debug("dac: ACODEC_SET_DACL_VOL\n");
if (vol.vol_ctrl_mute == 1) {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
temp |= AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
} else if ((vol.vol_ctrl < 0) | (vol.vol_ctrl > 32))
printf("dac-L: Only support range 0 [mute] ~ 32 [maximum]\n");
else {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1) & ~AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK;
temp |= DAC_VOL_L(vol.vol_ctrl);
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1, temp);
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
temp &= AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_OFF;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
}
break;
case ACODEC_SET_DACR_VOL:
debug("dac: ACODEC_SET_DACR_VOL\n");
if (vol.vol_ctrl_mute == 1) {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
temp |= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
} else if ((vol.vol_ctrl < 0) | (vol.vol_ctrl > 32))
printf("dac-R: Only support range 0 [mute] ~ 32 [maximum]\n");
else {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1) & ~AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK;
temp |= DAC_VOL_R(vol.vol_ctrl);
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1, temp);
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
temp &= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFF;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
}
break;
case ACODEC_SET_DACL_MUTE:
debug("dac: ACODEC_SET_DACL_MUTE, val=%d\n", val);
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
if (val == 0)
temp &= AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_OFF;
else
temp |= AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
break;
case ACODEC_SET_DACR_MUTE:
debug("dac: ACODEC_SET_DACR_MUTE, val=%d\n", val);
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
if (val == 0)
temp &= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFF;
else
temp |= AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2, temp);
break;
case ACODEC_GET_DACL_VOL:
debug("dac: ACODEC_GET_DACL_VOL\n");
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
if (temp & AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_MASK) {
vol.vol_ctrl = 0;
vol.vol_ctrl_mute = 1;
} else {
temp = ((dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
& AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK) + 1) / CV182x_DAC_VOL_STEP;
vol.vol_ctrl = temp;
vol.vol_ctrl_mute = 0;
}
//_/ if (copy_to_user(argp, &vol, sizeof(vol)))
//_/ printf("failed to return DACL vol\n");
break;
case ACODEC_GET_DACR_VOL:
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2);
debug("dac: ACODEC_GET_DACR_VOL, txdac_ana2=0x%x\n", temp);
if (temp & AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_MASK) {
vol.vol_ctrl = 0;
vol.vol_ctrl_mute = 1;
} else {
temp = (((dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1)
& AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK) >> 16) + 1) / CV182x_DAC_VOL_STEP;
vol.vol_ctrl = temp;
vol.vol_ctrl_mute = 0;
}
//_/ if (copy_to_user(argp, &vol, sizeof(vol)))
//_/ printf("failed to return DACR vol\n");
break;
case ACODEC_SET_PD_DACL:
debug("dac: ACODEC_SET_PD_DACL, val=%d\n", val);
if (val == 0) {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
temp &= AUDIO_PHY_REG_TXDAC_EN_ON | AUDIO_PHY_REG_I2S_RX_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, temp);
} else {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
temp &= AUDIO_PHY_REG_TXDAC_EN_OFF & AUDIO_PHY_REG_I2S_RX_EN_OFF;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, temp);
}
break;
case ACODEC_SET_PD_DACR:
debug("dac: ACODEC_SET_PD_DACR, val=%d\n", val);
if (val == 0) {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
temp &= AUDIO_PHY_REG_TXDAC_EN_ON | AUDIO_PHY_REG_I2S_RX_EN_ON;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, temp);
} else {
temp = dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0);
temp &= AUDIO_PHY_REG_TXDAC_EN_OFF & AUDIO_PHY_REG_I2S_RX_EN_OFF;
dac_write_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0, temp);
}
break;
case ACODEC_SET_DAC_DE_EMPHASIS:
debug("dac: ACODEC_SET_DAC_DE_EMPHASIS is not support\n");
break;
default:
printf("%s, received unsupported cmd=%u\n", __func__, cmd);
break;
}
return 0;
}
static void dump_182xdac_reg(struct cv182xdac *dac)
{
#ifdef __DEBUG__
printf("AUDIO_PHY_TXDAC_CTRL0 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL0));
printf("AUDIO_PHY_TXDAC_CTRL1 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_CTRL1));
printf("AUDIO_PHY_TXDAC_AFE0 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE0));
printf("AUDIO_PHY_TXDAC_AFE1 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_AFE1));
printf("AUDIO_PHY_TXDAC_ANA0 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA0));
printf("AUDIO_PHY_TXDAC_ANA1 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA1));
printf("AUDIO_PHY_TXDAC_ANA2 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA2));
printf("status : \n");
printf("AUDIO_PHY_TXDAC_ANA3 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_TXDAC_ANA3));
printf("AUDIO_PHY_RXADC_STATUS = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_RXADC_STATUS));
printf("AUDIO_PHY_RXADC_ANA1 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_RXADC_ANA1));
printf("AUDIO_PHY_RXADC_ANA4 = 0x%x \n", dac_read_reg(dac->dac_base, AUDIO_PHY_RXADC_ANA4));
#endif
}
int cvitekdac_device_init(struct cvitekdac_priv *priv)
{
return 0;
}
int cvitekdac_init(struct cvitekdac_priv *priv, int sample_rate, int channel)
{
dac = &g_dac;
dac->dac_base = (volatile u32 *)(0x0300A000);
cv182xdac_shutdown();
cv182xdac_hw_params(dac, channel, sample_rate);
cv182xdac_on(dac);
dump_182xdac_reg(dac);
return 0;
}
int cvitekub_dac_close(struct udevice *dev)
{
cv182xdac_shutdown();
return 0;
}
static int cvitekub_dac_set_params(struct udevice *dev, int interface, int rate,
int mclk_freq, int bits_per_sample, uint channels)
{
struct cvitekdac_priv *priv = dev_get_priv(dev);
return cvitekdac_init(priv, rate, channels);
}
static int cvitekub_dac_probe(struct udevice *dev)
{
struct cvitekdac_priv *priv = dev_get_priv(dev);
int ret = 0;
priv->dev = dev;
ret = cvitekdac_device_init(priv);
if (ret < 0) {
printf("%s:codec chip init failed\n", __func__);
return ret;
}
printf("%s\n", __func__);
return 0;
}
static const struct audio_codec_ops cvitekub_dac_ops = {
.set_params = cvitekub_dac_set_params,
.codec_close = cvitekub_dac_close,
};
static const struct udevice_id cvitekub_dac_ids[] = {
{ .compatible = "cvitek,cv182xadac" },
{ }
};
U_BOOT_DRIVER(cvitekub_dac) = {
.name = "cvitekub_dac",
.id = UCLASS_AUDIO_CODEC,
.of_match = cvitekub_dac_ids,
.probe = cvitekub_dac_probe,
.ops = &cvitekub_dac_ops,
.priv_auto = sizeof(struct cvitekdac_priv),
};
u-boot-2021.10/drivers/cvi_sound/cvi-dac.h 0 → 100644
View file @ 1f388afc
#ifndef __CVI_DAC_H__
#define __CVI_DAC_H__
#include <linux/types.h>
#include <stdbool.h>
#include <stdio.h>
#include <linux/delay.h>
#define CV182X_ADC_BASE_OFFSET 0x100
#define AUDIO_PHY_TXDAC_CTRL0 0x0
#define AUDIO_PHY_TXDAC_CTRL1 0x4
#define AUDIO_PHY_TXDAC_STATUS 0x8
#define AUDIO_PHY_TXDAC_AFE0 0xc
#define AUDIO_PHY_TXDAC_AFE1 0x10
#define AUDIO_PHY_TXDAC_ANA0 0x20
#define AUDIO_PHY_TXDAC_ANA1 0x24
#define AUDIO_PHY_TXDAC_ANA2 0x28
#define AUDIO_PHY_TXDAC_ANA3 0x2c
#define AUDIO_PHY_TXDAC_TEST 0x30
#define AUDIO_PHY_RXADC_CTRL0 (0x100 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_CTRL1 (0x104 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_STATUS (0x108 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_CLK (0x10c - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA0 (0x110 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA1 (0x114 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA2 (0x118 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA3 (0x11c - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA4 (0x120 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA5 (0x124 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_RXADC_ANA6 (0x128 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_GPIO_ANA (0x12c - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_SPARE_0 (0xff0 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_SPARE_1 (0xff4 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_SPARE_RO (0xff8 - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_DATE_CODE (0xffc - CV182X_ADC_BASE_OFFSET)
#define AUDIO_PHY_REG_TXDAC_EN 0x0
#define AUDIO_PHY_REG_TXDAC_EN_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_EN_MASK 0x1
#define AUDIO_PHY_REG_TXDAC_EN_BITS 0x1
#define AUDIO_PHY_REG_I2S_RX_EN 0x0
#define AUDIO_PHY_REG_I2S_RX_EN_OFFSET 1
#define AUDIO_PHY_REG_I2S_RX_EN_MASK 0x2
#define AUDIO_PHY_REG_I2S_RX_EN_BITS 0x1
#define AUDIO_PHY_REG_TXDAC_EN_ON 0x1
#define AUDIO_PHY_REG_TXDAC_EN_OFF 0xFFFFFFFE
#define AUDIO_PHY_REG_I2S_RX_EN_ON 0x2
#define AUDIO_PHY_REG_I2S_RX_EN_OFF 0xFFFFFFFD
#define AUDIO_PHY_REG_TXDAC_CIC_OPT 0x4
#define AUDIO_PHY_REG_TXDAC_CIC_OPT_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_CIC_OPT_MASK 0x1
#define AUDIO_PHY_REG_TXDAC_CIC_OPT_BITS 0x1
#define TXDAC_CIC_DS_64 0xFFFFFFFE
#define TXDAC_CIC_DS_128 0x00000001
#define TXDAC_CIC_DS_256 0x00000002
#define TXDAC_CIC_DS_512 0x00000003
#define AUDIO_PHY_REG_TXDAC_FSM_SRC_SEL 0x4
#define AUDIO_PHY_REG_TXDAC_FSM_SRC_SEL_OFFSET 1
#define AUDIO_PHY_REG_TXDAC_FSM_SRC_SEL_MASK 0x2
#define AUDIO_PHY_REG_TXDAC_FSM_SRC_SEL_BITS 0x1
#define AUDIO_PHY_REG_TXDAC_INIT_DLY_CNT_MASK 0x3f
#define AUDIO_PHY_REG_TXDAC_DEM_TYPE 0x4
#define AUDIO_PHY_REG_TXDAC_DEM_TYPE_OFFSET 4
#define AUDIO_PHY_REG_TXDAC_DEM_TYPE_MASK 0x30
#define AUDIO_PHY_REG_TXDAC_DEM_TYPE_BITS 0x2
#define AUDIO_PHY_REG_TXDAC_DSM_OPT 0x4
#define AUDIO_PHY_REG_TXDAC_DSM_OPT_OFFSET 8
#define AUDIO_PHY_REG_TXDAC_DSM_OPT_MASK 0x100
#define AUDIO_PHY_REG_TXDAC_DSM_OPT_BITS 0x1
#define AUDIO_PHY_REG_TXDAC_DITHER_OPT 0x4
#define AUDIO_PHY_REG_TXDAC_DITHER_OPT_OFFSET 12
#define AUDIO_PHY_REG_TXDAC_DITHER_OPT_MASK 0x7000
#define AUDIO_PHY_REG_TXDAC_DITHER_OPT_BITS 0x3
#define AUDIO_PHY_REG_TXDAC_FSM 0x8
#define AUDIO_PHY_REG_TXDAC_FSM_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_FSM_MASK 0x7
#define AUDIO_PHY_REG_TXDAC_FSM_BITS 0x3
#define AUDIO_PHY_REG_TXDAC_AFE_FSM 0x8
#define AUDIO_PHY_REG_TXDAC_AFE_FSM_OFFSET 4
#define AUDIO_PHY_REG_TXDAC_AFE_FSM_MASK 0x70
#define AUDIO_PHY_REG_TXDAC_AFE_FSM_BITS 0x3
#define AUDIO_PHY_REG_TXDAC_GAIN0 0x8
#define AUDIO_PHY_REG_TXDAC_GAIN0_OFFSET 8
#define AUDIO_PHY_REG_TXDAC_GAIN0_MASK 0x1ff00
#define AUDIO_PHY_REG_TXDAC_GAIN0_BITS 0x9
#define AUDIO_PHY_REG_TXDAC_GAIN1 0x8
#define AUDIO_PHY_REG_TXDAC_GAIN1_OFFSET 20
#define AUDIO_PHY_REG_TXDAC_GAIN1_MASK 0x1ff00000
#define AUDIO_PHY_REG_TXDAC_GAIN1_BITS 0x9
#define AUDIO_PHY_REG_TXDAC_TICK_NUM 0xc
#define AUDIO_PHY_REG_TXDAC_TICK_NUM_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_TICK_NUM_MASK 0xff
#define AUDIO_PHY_REG_TXDAC_TICK_NUM_BITS 0x8
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_0 0x10
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_0_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_0_MASK 0x1ff
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_0_BITS 0x9
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_1 0x10
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_1_OFFSET 16
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_1_MASK 0x1ff0000
#define AUDIO_PHY_REG_TXDAC_GAIN_UB_1_BITS 0x9
#define AUDIO_PHY_REG_TXDAC_RAMP_BP 0x10
#define AUDIO_PHY_REG_TXDAC_RAMP_BP_OFFSET 28
#define AUDIO_PHY_REG_TXDAC_RAMP_BP_MASK 0x10000000
#define AUDIO_PHY_REG_TXDAC_RAMP_BP_BITS 0x1
#define AUDIO_PHY_REG_ADDI_TXDAC 0x20
#define AUDIO_PHY_REG_ADDI_TXDAC_OFFSET 0
#define AUDIO_PHY_REG_ADDI_TXDAC_MASK 0x1
#define AUDIO_PHY_REG_ADDI_TXDAC_BITS 0x1
#define ADDI_TXDAC_GAIN_RATIO_1 0xFFFFFFFE
#define ADDI_TXDAC_GAIN_RATIO_2_5 0x00000001
#define AUDIO_PHY_REG_TSEL_TXDAC 0x20
#define AUDIO_PHY_REG_TSEL_TXDAC_OFFSET 4
#define AUDIO_PHY_REG_TSEL_TXDAC_MASK 0x30
#define AUDIO_PHY_REG_TSEL_TXDAC_BITS 0x2
#define AUDIO_PHY_REG_VSEL_TXDAC 0x20
#define AUDIO_PHY_REG_VSEL_TXDAC_OFFSET 8
#define AUDIO_PHY_REG_VSEL_TXDAC_MASK 0x300
#define AUDIO_PHY_REG_VSEL_TXDAC_BITS 0x2
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_VAL 0x24
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_VAL_OFFSET 0
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_VAL_MASK 0x1
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_VAL 0x24
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_VAL_OFFSET 1
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_VAL_MASK 0x2
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_EN 0x24
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_EN_OFFSET 16
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_EN_MASK 0x10000
#define AUDIO_PHY_REG_DA_EN_TXDAC_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_EN 0x24
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_EN_OFFSET 17
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_EN_MASK 0x20000
#define AUDIO_PHY_REG_DA_END2US_TXDAC_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_VAL 0x28
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_VAL_OFFSET 0
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_VAL_MASK 0xff
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_VAL_BITS 0x8
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_VAL 0x28
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_VAL_OFFSET 8
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_VAL_MASK 0xff00
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_VAL_BITS 0x8
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN 0x28
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_OFFSET 16
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_MASK 0x10000
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN 0x28
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFFSET 17
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_MASK 0x20000
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_ON 0x10000
#define AUDIO_PHY_REG_DA_DEML_TXDAC_OW_EN_OFF 0xFFFEFFFF
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_ON 0x20000
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_OW_EN_OFF 0xFFFDFFFF
#define AUDIO_PHY_REG_DA_EN_TXDAAUDIO_PHY_RXADC_ANA2C_STATUS 0x2c
#define AUDIO_PHY_REG_DA_EN_TXDAC_STATUS_OFFSET 0
#define AUDIO_PHY_REG_DA_EN_TXDAC_STATUS_MASK 0x1
#define AUDIO_PHY_REG_DA_EN_TXDAC_STATUS_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_TXDAC_STATUS 0x2c
#define AUDIO_PHY_REG_DA_END2US_TXDAC_STATUS_OFFSET 1
#define AUDIO_PHY_REG_DA_END2US_TXDAC_STATUS_MASK 0x2
#define AUDIO_PHY_REG_DA_END2US_TXDAC_STATUS_BITS 0x1
#define AUDIO_PHY_REG_DA_DEML_TXDAC_STATUS 0x2c
#define AUDIO_PHY_REG_DA_DEML_TXDAC_STATUS_OFFSET 16
#define AUDIO_PHY_REG_DA_DEML_TXDAC_STATUS_MASK 0xff0000
#define AUDIO_PHY_REG_DA_DEML_TXDAC_STATUS_BITS 0x8
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_STATUS 0x2c
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_STATUS_OFFSET 24
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_STATUS_MASK 0xff000000
#define AUDIO_PHY_REG_DA_DEMR_TXDAC_STATUS_BITS 0x8
#define AUDIO_PHY_REG_TXDAC_I2S_BP 0x30
#define AUDIO_PHY_REG_TXDAC_I2S_BP_OFFSET 0
#define AUDIO_PHY_REG_TXDAC_I2S_BP_MASK 0x1
#define AUDIO_PHY_REG_TXDAC_I2S_BP_BITS 0x1
#define AUDIO_PHY_REG_RXADC_TO_TXDAC 0x30
#define AUDIO_PHY_REG_RXADC_TO_TXDAC_OFFSET 1
#define AUDIO_PHY_REG_RXADC_TO_TXDAC_MASK 0x2
#define AUDIO_PHY_REG_RXADC_TO_TXDAC_BITS 0x1
#define AUDIO_PHY_REG_RXADC_EN 0x100
#define AUDIO_PHY_REG_RXADC_EN_OFFSET 0
#define AUDIO_PHY_REG_RXADC_EN_MASK 0x1
#define AUDIO_PHY_REG_RXADC_EN_BITS 0x1
#define AUDIO_PHY_REG_I2S_TX_EN 0x100
#define AUDIO_PHY_REG_I2S_TX_EN_OFFSET 1
#define AUDIO_PHY_REG_I2S_TX_EN_MASK 0x2
#define AUDIO_PHY_REG_I2S_TX_EN_BITS 0x1
#define AUDIO_PHY_REG_RXADC_EN_ON 0x1
#define AUDIO_PHY_REG_RXADC_EN_OFF 0xFFFFFFFE
#define AUDIO_PHY_REG_I2S_TX_EN_ON 0x2
#define AUDIO_PHY_REG_I2S_TX_EN_OFF 0xFFFFFFFD
#define AUDIO_PHY_REG_RXADC_CIC_OPT 0x104
#define AUDIO_PHY_REG_RXADC_CIC_OPT_OFFSET 0
#define AUDIO_PHY_REG_RXADC_CIC_OPT_MASK 0x1
#define AUDIO_PHY_REG_RXADC_CIC_OPT_BITS 0x1
#define RXADC_CIC_DS_64 0xFFFFFFFE
#define RXADC_CIC_DS_128 0x00000001
#define RXADC_CIC_DS_256 0x00000002
#define RXADC_CIC_DS_512 0x00000003
#define AUDIO_PHY_REG_RXADC_FSM_SRC_SEL 0x104
#define AUDIO_PHY_REG_RXADC_FSM_SRC_SEL_OFFSET 1
#define AUDIO_PHY_REG_RXADC_FSM_SRC_SEL_MASK 0x2
#define AUDIO_PHY_REG_RXADC_FSM_SRC_SEL_BITS 0x1
#define AUDIO_PHY_REG_RXADC_CHN_SWAP 0x104
#define AUDIO_PHY_REG_RXADC_CHN_SWAP_OFFSET 2
#define AUDIO_PHY_REG_RXADC_CHN_SWAP_MASK 0x4
#define AUDIO_PHY_REG_RXADC_CHN_SWAP_BITS 0x1
#define AUDIO_PHY_REG_RXADC_SINGLE 0x104
#define AUDIO_PHY_REG_RXADC_SINGLE_OFFSET 3
#define AUDIO_PHY_REG_RXADC_SINGLE_MASK 0x8
#define AUDIO_PHY_REG_RXADC_SINGLE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_DCB_OPT 0x104
#define AUDIO_PHY_REG_RXADC_DCB_OPT_OFFSET 4
#define AUDIO_PHY_REG_RXADC_DCB_OPT_MASK 0x70
#define AUDIO_PHY_REG_RXADC_DCB_OPT_BITS 0x3
#define AUDIO_PHY_REG_RXADC_IGR_INIT 0x104
#define AUDIO_PHY_REG_RXADC_IGR_INIT_OFFSET 8
#define AUDIO_PHY_REG_RXADC_IGR_INIT_MASK 0x100
#define AUDIO_PHY_REG_RXADC_IGR_INIT_BITS 0x1
#define AUDIO_ADC_IGR_INIT_EN 0x100
#define AUDIO_ADC_IGR_INIT_OFF 0xFFFFFEFF
#define AUDIO_PHY_REG_RXADC_CLK_FORCE_EN 0x104
#define AUDIO_PHY_REG_RXADC_CLK_FORCE_EN_OFFSET 9
#define AUDIO_PHY_REG_RXADC_CLK_FORCE_EN_MASK 0x200
#define AUDIO_PHY_REG_RXADC_CLK_FORCE_EN_BITS 0x1
#define AUDIO_PHY_REG_RXADC_CIC0_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_CIC0_INIT_DONE_OFFSET 0
#define AUDIO_PHY_REG_RXADC_CIC0_INIT_DONE_MASK 0x1
#define AUDIO_PHY_REG_RXADC_CIC0_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_FIR1_0_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_FIR1_0_INIT_DONE_OFFSET 1
#define AUDIO_PHY_REG_RXADC_FIR1_0_INIT_DONE_MASK 0x2
#define AUDIO_PHY_REG_RXADC_FIR1_0_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_FIR2_0_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_FIR2_0_INIT_DONE_OFFSET 2
#define AUDIO_PHY_REG_RXADC_FIR2_0_INIT_DONE_MASK 0x4
#define AUDIO_PHY_REG_RXADC_FIR2_0_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_CIC1_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_CIC1_INIT_DONE_OFFSET 4
#define AUDIO_PHY_REG_RXADC_CIC1_INIT_DONE_MASK 0x10
#define AUDIO_PHY_REG_RXADC_CIC1_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_FIR1_1_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_FIR1_1_INIT_DONE_OFFSET 5
#define AUDIO_PHY_REG_RXADC_FIR1_1_INIT_DONE_MASK 0x20
#define AUDIO_PHY_REG_RXADC_FIR1_1_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_FIR2_1_INIT_DONE 0x108
#define AUDIO_PHY_REG_RXADC_FIR2_1_INIT_DONE_OFFSET 6
#define AUDIO_PHY_REG_RXADC_FIR2_1_INIT_DONE_MASK 0x40
#define AUDIO_PHY_REG_RXADC_FIR2_1_INIT_DONE_BITS 0x1
#define AUDIO_PHY_REG_RXADC_FSM 0x108
#define AUDIO_PHY_REG_RXADC_FSM_OFFSET 8
#define AUDIO_PHY_REG_RXADC_FSM_MASK 0x700
#define AUDIO_PHY_REG_RXADC_FSM_BITS 0x3
#define AUDIO_RXADC_SCK_DIV_MASK 0x0000FF00
#define RXADC_SCK_DIV(l) ((l-1) << 8)
#define AUDIO_RXADC_DLYEN_MASK 0x00FF0000
#define RXADC_DLYEN(l) (l << 16)
#define AUDIO_PHY_REG_GSTEPL_RXPGA 0x110
#define AUDIO_PHY_REG_GSTEPL_RXPGA_OFFSET 0
#define AUDIO_PHY_REG_GSTEPL_RXPGA_MASK 0x1fff
#define AUDIO_PHY_REG_GSTEPL_RXPGA_BITS 0xd
#define AUDIO_PHY_REG_G6DBL_RXPGA 0x110
#define AUDIO_PHY_REG_G6DBL_RXPGA_OFFSET 13
#define AUDIO_PHY_REG_G6DBL_RXPGA_MASK 0x2000
#define AUDIO_PHY_REG_G6DBL_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_GAINL_RXADC 0x110
#define AUDIO_PHY_REG_GAINL_RXADC_OFFSET 14
#define AUDIO_PHY_REG_GAINL_RXADC_MASK 0xc000
#define AUDIO_PHY_REG_GAINL_RXADC_BITS 0x2
#define AUDIO_PHY_REG_GSTEPR_RXPGA 0x110
#define AUDIO_PHY_REG_GSTEPR_RXPGA_OFFSET 16
#define AUDIO_PHY_REG_GSTEPR_RXPGA_MASK 0x1fff0000
#define AUDIO_PHY_REG_GSTEPR_RXPGA_BITS 0xd
#define AUDIO_PHY_REG_G6DBR_RXPGA 0x110
#define AUDIO_PHY_REG_G6DBR_RXPGA_OFFSET 29
#define AUDIO_PHY_REG_G6DBR_RXPGA_MASK 0x20000000
#define AUDIO_PHY_REG_G6DBR_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_GAINR_RXADC 0x110
#define AUDIO_PHY_REG_GAINR_RXADC_OFFSET 30
#define AUDIO_PHY_REG_GAINR_RXADC_MASK 0xc0000000
#define AUDIO_PHY_REG_GAINR_RXADC_BITS 0x2
#define AUDIO_PHY_REG_ADC_VOLL_MASK 0xffff
#define AUDIO_PHY_REG_ADC_VOLR_MASK 0xffff0000
#define DAC_VOL_L_MASK 0x000001FF
#define CV182x_DAC_VOL_STEP 0x8
#define DAC_VOL_L(V) (V == 0 ? 0 : (V * CV182x_DAC_VOL_STEP) - 1)
#define DAC_VOL_R(V) ((V == 0 ? 0 : (V * CV182x_DAC_VOL_STEP) - 1) << 16)
#define ADC_VOL_GAIN_0 0x0001 /* 0dB */
#define ADC_VOL_GAIN_1 0x0002 /* 2dB */
#define ADC_VOL_GAIN_2 0x0004 /* 4dB */
#define ADC_VOL_GAIN_3 0x0008 /* 6dB */
#define ADC_VOL_GAIN_4 0x0010 /* 8dB */
#define ADC_VOL_GAIN_5 0x0020 /* 10dB */
#define ADC_VOL_GAIN_6 0x0040 /* 12dB */
#define ADC_VOL_GAIN_7 0x0080 /* 14dB */
#define ADC_VOL_GAIN_8 0x0100 /* 16dB */
#define ADC_VOL_GAIN_9 0x0200 /* 18dB */
#define ADC_VOL_GAIN_10 0x0400 /* 20dB */
#define ADC_VOL_GAIN_11 0x0800 /* 22dB */
#define ADC_VOL_GAIN_12 0x1000 /* 24dB */
#define ADC_VOL_GAIN_13 0x2400 /* 26dB */
#define ADC_VOL_GAIN_14 0x2800 /* 28dB */
#define ADC_VOL_GAIN_15 0x3000 /* 30dB */
#define ADC_VOL_GAIN_16 0x6400 /* 32dB */
#define ADC_VOL_GAIN_17 0x6800 /* 34dB */
#define ADC_VOL_GAIN_18 0x7000 /* 36dB */
#define ADC_VOL_GAIN_19 0xA400 /* 38dB */
#define ADC_VOL_GAIN_20 0xA800 /* 40dB */
#define ADC_VOL_GAIN_21 0xB000 /* 42dB */
#define ADC_VOL_GAIN_22 0xE400 /* 44dB */
#define ADC_VOL_GAIN_23 0xE800 /* 46dB */
#define ADC_VOL_GAIN_24 0xF000 /* 48dB */
#define ADC_VOL_L(V) (ADC_VOL_GAIN_##V)
#define ADC_VOL_R(V) (ADC_VOL_GAIN_##V << 16)
#define AUDIO_PHY_REG_GAINL_STATUS 0x114
#define AUDIO_PHY_REG_GAINL_STATUS_OFFSET 0
#define AUDIO_PHY_REG_GAINL_STATUS_MASK 0xffff
#define AUDIO_PHY_REG_GAINL_STATUS_BITS 0x10
#define AUDIO_PHY_REG_GAINR_STATUS 0x114
#define AUDIO_PHY_REG_GAINR_STATUS_OFFSET 16
#define AUDIO_PHY_REG_GAINR_STATUS_MASK 0xffff0000
#define AUDIO_PHY_REG_GAINR_STATUS_BITS 0x10
#define AUDIO_PHY_REG_MUTEL_RXPGA 0x118
#define AUDIO_PHY_REG_MUTEL_RXPGA_OFFSET 0
#define AUDIO_PHY_REG_MUTEL_RXPGA_MASK 0x1
#define AUDIO_PHY_REG_MUTEL_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_MUTER_RXPGA 0x118
#define AUDIO_PHY_REG_MUTER_RXPGA_OFFSET 1
#define AUDIO_PHY_REG_MUTER_RXPGA_MASK 0x2
#define AUDIO_PHY_REG_MUTER_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_DIFF_EN_RXPGA 0x118
#define AUDIO_PHY_REG_DIFF_EN_RXPGA_OFFSET 16
#define AUDIO_PHY_REG_DIFF_EN_RXPGA_MASK 0x10000
#define AUDIO_PHY_REG_DIFF_EN_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_TRISTATE_RXPGA 0x118
#define AUDIO_PHY_REG_TRISTATE_RXPGA_OFFSET 17
#define AUDIO_PHY_REG_TRISTATE_RXPGA_MASK 0x20000
#define AUDIO_PHY_REG_TRISTATE_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_MUTEL_ON 0x1
#define AUDIO_PHY_REG_MUTEL_OFF 0xFFFFFFFE
#define AUDIO_PHY_REG_MUTER_ON 0x2
#define AUDIO_PHY_REG_MUTER_OFF 0xFFFFFFFD
#define AUDIO_PHY_REG_ADDI_RXADC 0x11c
#define AUDIO_PHY_REG_ADDI_RXADC_OFFSET 0
#define AUDIO_PHY_REG_ADDI_RXADC_MASK 0x1
#define AUDIO_PHY_REG_ADDI_RXADC_BITS 0x1
#define AUDIO_PHY_REG_CKSEL_RXADC 0x11c
#define AUDIO_PHY_REG_CKSEL_RXADC_OFFSET 1
#define AUDIO_PHY_REG_CKSEL_RXADC_MASK 0x2
#define AUDIO_PHY_REG_CKSEL_RXADC_BITS 0x1
#define AUDIO_PHY_REG_EN_ASAR_I_RXADC 0x11c
#define AUDIO_PHY_REG_EN_ASAR_I_RXADC_OFFSET 2
#define AUDIO_PHY_REG_EN_ASAR_I_RXADC_MASK 0x4
#define AUDIO_PHY_REG_EN_ASAR_I_RXADC_BITS 0x1
#define AUDIO_PHY_REG_EN_ASAR_Q_RXADC 0x11c
#define AUDIO_PHY_REG_EN_ASAR_Q_RXADC_OFFSET 3
#define AUDIO_PHY_REG_EN_ASAR_Q_RXADC_MASK 0x8
#define AUDIO_PHY_REG_EN_ASAR_Q_RXADC_BITS 0x1
#define AUDIO_PHY_REG_DEM_TYPE_RXADC 0x11c
#define AUDIO_PHY_REG_DEM_TYPE_RXADC_OFFSET 4
#define AUDIO_PHY_REG_DEM_TYPE_RXADC_MASK 0x30
#define AUDIO_PHY_REG_DEM_TYPE_RXADC_BITS 0x2
#define AUDIO_PHY_REG_CTUNE_RXADC 0x11c
#define AUDIO_PHY_REG_CTUNE_RXADC_OFFSET 8
#define AUDIO_PHY_REG_CTUNE_RXADC_MASK 0xf00
#define AUDIO_PHY_REG_CTUNE_RXADC_BITS 0x4
#define RXADC_CTUNE_MCLK_4096 (0xF << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define RXADC_CTUNE_MCLK_5644 (0xA << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define RXADC_CTUNE_MCLK_8192 (0x4 << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define RXADC_CTUNE_MCLK_11298 (0xD << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define RXADC_CTUNE_MCLK_12288 (0xC << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define RXADC_CTUNE_MCLK_16384 (0x8 << AUDIO_PHY_REG_CTUNE_RXADC_OFFSET)
#define AUDIO_PHY_REG_EN_DITHER_RXADC 0x11c
#define AUDIO_PHY_REG_EN_DITHER_RXADC_OFFSET 12
#define AUDIO_PHY_REG_EN_DITHER_RXADC_MASK 0x1000
#define AUDIO_PHY_REG_EN_DITHER_RXADC_BITS 0x1
#define AUDIO_PHY_REG_RSTSDM_RXADC 0x11c
#define AUDIO_PHY_REG_RSTSDM_RXADC_OFFSET 13
#define AUDIO_PHY_REG_RSTSDM_RXADC_MASK 0x2000
#define AUDIO_PHY_REG_RSTSDM_RXADC_BITS 0x1
#define AUDIO_PHY_REG_EN_VCMT_RXADC 0x11c
#define AUDIO_PHY_REG_EN_VCMT_RXADC_OFFSET 14
#define AUDIO_PHY_REG_EN_VCMT_RXADC_MASK 0x4000
#define AUDIO_PHY_REG_EN_VCMT_RXADC_BITS 0x1
#define AUDIO_PHY_REG_VLDO0P9_RXADC 0x11c
#define AUDIO_PHY_REG_VLDO0P9_RXADC_OFFSET 16
#define AUDIO_PHY_REG_VLDO0P9_RXADC_MASK 0x30000
#define AUDIO_PHY_REG_VLDO0P9_RXADC_BITS 0x2
#define AUDIO_PHY_REG_VLDO12_RXADC 0x11c
#define AUDIO_PHY_REG_VLDO12_RXADC_OFFSET 18
#define AUDIO_PHY_REG_VLDO12_RXADC_MASK 0xc0000
#define AUDIO_PHY_REG_VLDO12_RXADC_BITS 0x2
#define AUDIO_PHY_REG_RNLVL_RXADC 0x11c
#define AUDIO_PHY_REG_RNLVL_RXADC_OFFSET 20
#define AUDIO_PHY_REG_RNLVL_RXADC_MASK 0x300000
#define AUDIO_PHY_REG_RNLVL_RXADC_BITS 0x2
#define AUDIO_PHY_REG_DA_EN_RXPGA_STATUS 0x120
#define AUDIO_PHY_REG_DA_EN_RXPGA_STATUS_OFFSET 0
#define AUDIO_PHY_REG_DA_EN_RXPGA_STATUS_MASK 0x1
#define AUDIO_PHY_REG_DA_EN_RXPGA_STATUS_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_RXPGA_STATUS 0x120
#define AUDIO_PHY_REG_DA_END2US_RXPGA_STATUS_OFFSET 1
#define AUDIO_PHY_REG_DA_END2US_RXPGA_STATUS_MASK 0x2
#define AUDIO_PHY_REG_DA_END2US_RXPGA_STATUS_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_RXADC_STATUS 0x120
#define AUDIO_PHY_REG_DA_EN_RXADC_STATUS_OFFSET 2
#define AUDIO_PHY_REG_DA_EN_RXADC_STATUS_MASK 0x4
#define AUDIO_PHY_REG_DA_EN_RXADC_STATUS_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_STATUS 0x120
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_STATUS_OFFSET 3
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_STATUS_MASK 0x8
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_STATUS_BITS 0x1
#define AUDIO_PHY_REG_AD_DOL_RXADC 0x120
#define AUDIO_PHY_REG_AD_DOL_RXADC_OFFSET 16
#define AUDIO_PHY_REG_AD_DOL_RXADC_MASK 0x70000
#define AUDIO_PHY_REG_AD_DOL_RXADC_BITS 0x3
#define AUDIO_PHY_REG_AD_DOR_RXADC 0x120
#define AUDIO_PHY_REG_AD_DOR_RXADC_OFFSET 20
#define AUDIO_PHY_REG_AD_DOR_RXADC_MASK 0x700000
#define AUDIO_PHY_REG_AD_DOR_RXADC_BITS 0x3
#define AUDIO_PHY_REG_TESTEN_AUDBIAS 0x124
#define AUDIO_PHY_REG_TESTEN_AUDBIAS_OFFSET 0
#define AUDIO_PHY_REG_TESTEN_AUDBIAS_MASK 0x1
#define AUDIO_PHY_REG_TESTEN_AUDBIAS_BITS 0x1
#define AUDIO_PHY_REG_TESTEN_RXPGA 0x124
#define AUDIO_PHY_REG_TESTEN_RXPGA_OFFSET 1
#define AUDIO_PHY_REG_TESTEN_RXPGA_MASK 0x2
#define AUDIO_PHY_REG_TESTEN_RXPGA_BITS 0x1
#define AUDIO_PHY_REG_TSEL_RXADC 0x124
#define AUDIO_PHY_REG_TSEL_RXADC_OFFSET 2
#define AUDIO_PHY_REG_TSEL_RXADC_MASK 0xc
#define AUDIO_PHY_REG_TSEL_RXADC_BITS 0x2
#define AUDIO_PHY_REG_AUD_VREF_FC 0x124
#define AUDIO_PHY_REG_AUD_VREF_FC_OFFSET 8
#define AUDIO_PHY_REG_AUD_VREF_FC_MASK 0x100
#define AUDIO_PHY_REG_AUD_VREF_FC_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_VAL 0x128
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_VAL_OFFSET 0
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_VAL_MASK 0x1
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_VAL 0x128
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_VAL_OFFSET 1
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_VAL_MASK 0x2
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_VAL 0x128
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_VAL_OFFSET 2
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_VAL_MASK 0x4
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_VAL 0x128
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_VAL_OFFSET 3
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_VAL_MASK 0x8
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_VAL_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_EN 0x128
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_EN_OFFSET 16
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_EN_MASK 0x10000
#define AUDIO_PHY_REG_DA_EN_RXPGA_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_EN 0x128
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_EN_OFFSET 17
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_EN_MASK 0x20000
#define AUDIO_PHY_REG_DA_END2US_RXPGA_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_EN 0x128
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_EN_OFFSET 18
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_EN_MASK 0x40000
#define AUDIO_PHY_REG_DA_EN_RXADC_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_EN 0x128
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_EN_OFFSET 19
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_EN_MASK 0x80000
#define AUDIO_PHY_REG_DA_EN_AUDBIAS_OW_EN_BITS 0x1
#define AUDIO_PHY_REG_GPIO_IEN 0x12c
#define AUDIO_PHY_REG_GPIO_IEN_OFFSET 0
#define AUDIO_PHY_REG_GPIO_IEN_MASK 0xf
#define AUDIO_PHY_REG_GPIO_IEN_BITS 0x4
#define AUDIO_PHY_REG_GPIO_DRV 0x12c
#define AUDIO_PHY_REG_GPIO_DRV_OFFSET 4
#define AUDIO_PHY_REG_GPIO_DRV_MASK 0xf0
#define AUDIO_PHY_REG_GPIO_DRV_BITS 0x4
#define AUDIO_PHY_REG_GPIO_C 0x12c
#define AUDIO_PHY_REG_GPIO_C_OFFSET 16
#define AUDIO_PHY_REG_GPIO_C_MASK 0xf0000
#define AUDIO_PHY_REG_GPIO_C_BITS 0x4
#define AUDIO_PHY_REG_SPARE0 0xff0
#define AUDIO_PHY_REG_SPARE0_OFFSET 0
#define AUDIO_PHY_REG_SPARE0_MASK 0xffffffff
#define AUDIO_PHY_REG_SPARE0_BITS 0x20
#define AUDIO_ADC_SCK_DIV_MASK 0x00ff0000
#define SPARE_SCK_DIV(l) ((l-1) << 16)
#define AUDIO_PHY_REG_SPARE1 0xff4
#define AUDIO_PHY_REG_SPARE1_OFFSET 0
#define AUDIO_PHY_REG_SPARE1_MASK 0xffff
#define AUDIO_PHY_REG_SPARE1_BITS 0x10
#define AUDIO_PHY_REG_SPARE_RO 0xff8
#define AUDIO_PHY_REG_SPARE_RO_OFFSET 0
#define AUDIO_PHY_REG_SPARE_RO_MASK 0xffffffff
#define AUDIO_PHY_REG_SPARE_RO_BITS 0x20
#define AUDIO_PHY_REG_DATE_CODE 0xffc
#define AUDIO_PHY_REG_DATE_CODE_OFFSET 0
#define AUDIO_PHY_REG_DATE_CODE_MASK 0xffffffff
#define AUDIO_PHY_REG_DATE_CODE_BITS 0x20
#define CVI_I2S_EN 0x18
#define CVI_I2S_CLK_CTRL0 0x60
#define CVI_I2S_CLK_CTRL1 0x64
#define CVI_I2S_MCLK_OUT_EN_MASK 0x00000080
#define CVI_I2S_MCLK_OUT_EN BIT(7)
#define CVI_I2S_MCLK_OUT_OFF 0xFFFFFF7F
#define CVI_I2S_AU_EN_MASK 0x00000100
#define CVI_I2S_AU_EN BIT(8)
#define CVI_I2S_AU_OFF 0xFFFFFEFF
#define CVI_I2S_MCLK_MASK 0x0000FFFF
#define CVI_I2S_MCLK_DIV(l) ((l << 0) & 0x0000FFFF)
#define ACODEC_SOFT_RESET_CTRL 1
#define ACODEC_SET_INPUT_VOL 2
#define ACODEC_SET_OUTPUT_VOL 3
#define ACODEC_GET_INPUT_VOL 4
#define ACODEC_GET_OUTPUT_VOL 5
#define ACODEC_SET_I2S1_FS 6
#define ACODEC_SET_MIXER_MIC 7
#define ACODEC_SET_GAIN_MICL 8
#define ACODEC_SET_GAIN_MICR 9
#define ACODEC_SET_DACL_VOL 10
#define ACODEC_SET_DACR_VOL 11
#define ACODEC_SET_ADCL_VOL 12
#define ACODEC_SET_ADCR_VOL 13
#define ACODEC_SET_MICL_MUTE 14
#define ACODEC_SET_MICR_MUTE 15
#define ACODEC_SET_DACL_MUTE 16
#define ACODEC_SET_DACR_MUTE 17
#define ACODEC_GET_GAIN_MICL 18
#define ACODEC_GET_GAIN_MICR 19
#define ACODEC_GET_DACL_VOL 20
#define ACODEC_GET_DACR_VOL 21
#define ACODEC_GET_ADCL_VOL 22
#define ACODEC_GET_ADCR_VOL 23
#define ACODEC_SET_PD_DACL 24
#define ACODEC_SET_PD_DACR 25
#define ACODEC_SET_PD_ADCL 26
#define ACODEC_SET_PD_ADCR 27
#define ACODEC_SET_PD_LINEINL 28
#define ACODEC_SET_PD_LINEINR 29
#define ACODEC_SET_DAC_DE_EMPHASIS 30
#define ACODEC_SET_ADC_HP_FILTER 31
#define CV182X_DAC_RESET 0xF7FFFFFF
#define CV182X_DAC_APB_RESET 0xEFFFFFFF
#define CV182X_ADC_RESET 0xDFFFFFFF
#define CV182X_ADC_APB_RESET 0xBFFFFFFF
#define CVI_DAC_FS_REG 0x00
#define CVI_DAC_FS_16_32 0x0
#define CVI_DAC_FS_32_64 0x1
#define CVI_DAC_FS_64_128 0x2
#define CVI_DAC_FS_128_192 0x3
#define CVI_DAC_CTRL_REG 0x04
#define CVI_DAC_PWDAR_MASK 0x00000001
#define CVI_DAC_PWDAR_NORMAL 0xFFFFFFFE
#define CVI_DAC_PWDAR_DOWN (1 << 0)
#define CVI_DAC_PWDAL_MASK 0x00000002
#define CVI_DAC_PWDAL_NORMAL 0xFFFFFFFD
#define CVI_DAC_PWDAL_DOWN (1 << 1)
#define CVI_DAC_EN_REF_DISABLE 0xFFFFFFFB
#define CVI_DAC_EN_REF_ENABLE (1 << 2)
#define CVI_DAC_DEN_ENABLE 0xFFFFFFF7
#define CVI_DAC_DEN_DISABLE (1 << 3)
#define CVI_DAC_AEN_ENABLE 0xFFFFFFEF
#define CVI_DAC_AEN_DISABLE (1 << 4)
#define CVI_DAC_STR_DISABLE 0xFFFFFFDF
#define CVI_DAC_STR_ENABLE (1 << 5)
#define CVI_DAC_DISTHER_DISABLE 0xFFFFFFBF
#define CVI_DAC_DISTHER_ENABLE (1 << 6)
#define CVI_DAC_MUTE_MODE 0xFFFFFCFF
#define CVI_DAC_DEMUTE_MODE (0x3 << 8)
#define CVI_DAC_CKINV_NODELAY 0xFFFFFBFF
#define CVI_DAC_CKINV_DELAY (1 << 10)
#define CVI_DAC_S_MASK 0xFFFF0FFF
#define CVI_DAC_S(v) (v << 12)
#define CVI_DAC_ZCD_DISABLE 0xFFFEFFFF
#define CVI_DAC_ZCD_ENABLE (1 << 16)
#define CVI_DAC_TEST_MODE_REG 0x08
#define CVI_DAC_TM_NORMAL 0x0
#define CVI_DAC_TM_DF 0x1 /* DAC digital filter test mode */
#define CVI_DAC_TM_SDM 0x2 /* DAC delta sigma modulator */
#define CVI_DAC_AIO_DA_REG 0x0C
#define CVI_DAV_AIO_ALL_GPIO 0x0
#define CVI_DAV_AIO_2CH 0x1
#define CVI_DAC_AS_LEVEL_REG 0x10
enum cv1835_codec_fs {
ACODEC_FS_8000 = 0x1,
ACODEC_FS_11025 = 0x2,
ACODEC_FS_12000 = 0x3,
ACODEC_FS_16000 = 0x4,
ACODEC_FS_22050 = 0x5,
ACODEC_FS_24000 = 0x6,
ACODEC_FS_32000 = 0x7,
ACODEC_FS_44100 = 0x8,
ACODEC_FS_48000 = 0x9,
ACODEC_FS_64000 = 0xa,
ACODEC_FS_96000 = 0xb,
ACODEC_FS_192000 = 0xc,
};
#define CVI_ADC_GSEL_REG 0x00
#define CVI_ADC_GSELR_MASK 0xFFFFFFE0
#define CVI_ADC_GSELR(v) (v << 0)
#define CVI_ADC_GSELL_MASK 0xFFFFE0FF
#define CVI_ADC_GSELL(v) (v << 8)
#define CVI_ADC_GSELR_MIC_MASK 0xFFF8FFFF
#define CVI_ADC_GSELR_MIC(v) (v << 16)
#define CVI_ADC_GSELL_MIC_MASK 0xF8FFFFFF
#define CVI_ADC_GSELL_MIC(v) (v << 24)
#define CVI_ADC_CTRL_REG 0x04
#define CVI_ADC_INSELR_LINE 0xFFFFFFFE /* bit[0] == 0*/
#define CVI_ADC_INSELR_MIC (1 << 0)
#define CVI_ADC_INSELL_LINE 0xFFFFFFFD /* bit[1] == 0*/
#define CVI_ADC_INSELL_MIC (1 << 1)
#define CVI_ADC_POWER_MASK 0xFFFCFF0C /* use to reset power on/off related bits */
#define CVI_ADC_ENADR_POWER_DOWN 0xFFFFFFFB /* bit[2] == 0*/
#define CVI_ADC_ENADR_NORMAL (1 << 2)
#define CVI_ADC_ENADL_POWER_DOWN 0xFFFFFFF7 /* bit[3] == 0*/
#define CVI_ADC_ENADL_NORMAL (1 << 3)
#define CVI_ADC_VREF_POWER_DOWN 0xFFFFFFEF /* bit[4] == 0*/
#define CVI_ADC_VERF_NORMAL (1 << 4)
#define CVI_ADC_ZCD_DISABLE 0xFFFFFFDF /* bit[5] == 0*/
#define CVI_ADC_ZCD_ENABLE (1 << 5)
#define CVI_ADC_HPR_BYPASS 0xFFFFFFBF /* bit[6] == 0*/
#define CVI_ADC_HPR_ENABLE (1 << 6)
#define CVI_ADC_HPL_BYPASS 0xFFFFFF7F /* bit[7] == 0*/
#define CVI_ADC_HPL_ENABLE (1 << 7)
#define CVI_ADC_OVRS_MASK 0xFFFCFFFF
#define CVI_ADC_OVRS(v) (v << 16)
#define CVI_ADC_OVTOP_REG 0x08
#define CVI_ADC_TEST_MODE_REG 0x0C
#define CVI_ADC_TM_NORMAL 0x0
#define CVI_ADC_TM_READ_ROM 0x2
#define CVI_ADC_TM_R_PCM 0x6
#define CVI_ADC_TM_L_PCM 0x7
#define CVI_ADC_RSEL_REG 0x10
#define CVI_ADC_FS_SEL_REG 0x14 /* ADMCLK/LRCK ratio */
#define CVI_ADC_RATIO_256 0x0
#define CVI_ADC_RATIO_512 0x1
#define CVI_ADC_RATIO_1024 0x2
#define CVI_ADC_DAGC_CTRL_REG 0x20 /* digital AGC control */
#define CVI_ADC_DAGC_DISABLE 0xFFFFFFFE /* bit[0] == 0 */
#define CVI_ADC_DAGC_ENABLE (1 << 0)
#define CVI_ADC_DAGC_RMS_MODE 0xFFFFFFFD /* bit[1] == 1 */
#define CVI_ADC_DAGC_PEAK_MODE (1 << 1)
#define CVI_ADC_DAGC_ZCD_DISABLE 0xFFFFFFFB /* bit[2] == 0 */
#define CVI_ADC_DAGC_ZCD_ENABLE (1 << 2)
#define CVI_ADC_DAGC_THOLD_REG 0x24
#define CVI_ADC_DAGC_THOLD_MASK 0xFFFFFF81
#define CVI_ADC_DAGC_THOLD(v) (v << 0) /* maximum is 0x7f, minimum is 0x01 */
#define CVI_ADC_DAGC_UPDATE_THOLD_MASK 0x8000FFFF
#define CVI_ADC_DAGC_UPDATE_THOLD(v) (v << 16) /* maximum is 0x7fff */
#define CVI_ADC_DAGC_ATTACKTIME_REG 0x28
#define CVI_ADC_DAGC_SRC_DM_REG 0x2C
#define CVI_SDC_DAGC_UPDATE_FREQ_MASK 0xFFFFF000
#define CVI_SDC_DAGC_UPDATE_FREQ(v) (v << 0)
#define CVI_ADC_DAGC_SRC_DM_MASK 0xFFFFCFFF
#define CVI_ADC_DAGC_SRC_DM_MONO_L (0 << 12)
#define CVI_ADC_DAGC_PGAG_REG 0x30
#define CVI_ADC_DAGC_PGAG_R 0x0000001F
#define CVI_ADC_DAGC_PGAG_L 0x00001F00
#define CVI_ADC_ADCO_REG 0x34
enum cv1835_mixer {
CVI_MIXER_LINEIN = 0x0,
CVI_MIXER_MIC_IN = 0x1,
};
struct cvi1835dac {
volatile u32 *dac_base;
};
struct cvi1835adc {
volatile u32 *adc_base;
};
struct cv182xdac {
volatile u32 *dac_base;
};
struct cv182xadc {
volatile u32 *adc_base;
volatile u32 *mclk_source;
};
struct cvi_vol_ctrl {
/* volume control, adc range: 0x00~0x1f, 0x17F:mute. dac range: 0x00~0x0f, 0x0f:mute */
unsigned int vol_ctrl;
/* adc/dac mute control, 1:mute, 0:unmute */
unsigned int vol_ctrl_mute;
};
static inline void dac_write_reg(volatile u32 *io_base, u32 reg, u32 val)
{
*(io_base + (reg / sizeof(u32))) = val;
}
static inline u32 dac_read_reg(volatile u32 *io_base, u32 reg)
{
return *(io_base + (reg / sizeof(u32)));
}
static inline void adc_write_reg(volatile u32 *io_base, u32 reg, u32 val)
{
*(io_base + (reg / sizeof(u32))) = val;
}
static inline u32 adc_read_reg(volatile u32 *io_base, u32 reg)
{
u32 val;
val = *(io_base + (reg / sizeof(u32)));
return val;
}
static inline void reset_write_reg(u32 val, volatile u32 *io_base)
{
*(io_base) = val;
}
static inline u32 reset_read_reg(volatile u32 *io_base)
{
return *(io_base);
}
static inline void arch_usleep(unsigned long useconds)
{
//usleep(useconds);
udelay(useconds);
}
/* while cv182x codecs transfer CIC between 64 and 128, need to reset codec first */
static inline void cv182x_reset_dac(void)
{
volatile u32 *reset_reg = (volatile u32 *)(0x03003008);
reset_write_reg((reset_read_reg(reset_reg) & CV182X_DAC_RESET), reset_reg);
arch_usleep(1000 * 10);
reset_write_reg((reset_read_reg(reset_reg) | ~CV182X_DAC_RESET), reset_reg);
}
static inline void cv182x_reset_adc(void)
{
u32 *reset_reg = (u32 *)(0x03003008);
reset_write_reg((reset_read_reg(reset_reg) & CV182X_ADC_RESET), reset_reg);
arch_usleep(1000 * 10);
reset_write_reg((reset_read_reg(reset_reg) | ~CV182X_ADC_RESET), reset_reg);
}
int cv182xdac_init(u32 rate, u32 chan_nr);
int cv182xdac_ioctl(u32 cmd, struct cvi_vol_ctrl vol, u32 val);
int cv182xadc_init(u32 rate);
int cv182xadc_ioctl(u32 cmd, struct cvi_vol_ctrl vol, u32 val);
int cv183xdac_init(u32 rate);
int cv183xdac_ioctl(u32 cmd, struct cvi_vol_ctrl vol, u32 val);
u32 cv1835adc_ioctl(u32 cmd, struct cvi_vol_ctrl vol, u32 val);
int cv1835adc_init(u32 rate);
#endif /*__CVI_DAC_H__*/
u-boot-2021.10/drivers/cvi_sound/cvi-i2s-uclass.c 0 → 100644
View file @ 1f388afc
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#define LOG_CATEGORY UCLASS_I2S
#include <dm/uclass.h>
#include <common.h>
#include <dm.h>
#include <i2s.h>
int i2s_tx_data(struct udevice *dev, void *data, uint data_size)
{
struct i2s_ops *ops = i2s_get_ops(dev);
if (!ops->tx_data)
return -ENOSYS;
return ops->tx_data(dev, data, data_size);
}
UCLASS_DRIVER(i2s) = {
.id = UCLASS_I2S,
.name = "i2s",
.per_device_auto = sizeof(struct i2s_uc_priv),
};
u-boot-2021.10/drivers/cvi_sound/cvi-i2s.c 0 → 100644
View file @ 1f388afc
#include <common.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
#include <time.h>
#include <dm/device.h>
#include <asm/io.h>
#include <linux/delay.h>
#include "cvi-i2s.h"
#define AMP_PWR_GPIO_BASE 0x05021000
#define AMP_PWR_GPIO_INOUT 0x004
#define AMP_PWR_GPIO_PN 0x000
void i2s_reg_debug(struct i2s_tdm_regs *i2s_reg, struct i2s_sys_regs *i2s_sys_reg)
{
#ifdef __DEBUG__
printf("[i2s_tdm_reg]:\n");
printf("blk_mode_setting:0x%x\n", readl(&i2s_reg->blk_mode_setting));
printf("frame_setting:0x%x\n", readl(&i2s_reg->frame_setting));
printf("slot_setting1:0x%x\n", readl(&i2s_reg->slot_setting1));
printf("slot_setting2:0x%x\n", readl(&i2s_reg->slot_setting2));
printf("data_format:0x%x\n", readl(&i2s_reg->data_format));
printf("blk_cfg:0x%x\n", readl(&i2s_reg->blk_cfg));
printf("i2s_enable:0x%x\n", readl(&i2s_reg->i2s_enable));
printf("i2s_reset:0x%x\n", readl(&i2s_reg->i2s_reset));
printf("i2s_int_en:0x%x\n", readl(&i2s_reg->i2s_int_en));
printf("i2s_int:0x%x\n", readl(&i2s_reg->i2s_int));
printf("fifo_threshold:0x%x\n", readl(&i2s_reg->fifo_threshold));
printf("fifo_reset:0x%x\n", readl(&i2s_reg->fifo_reset));
printf("i2s_clk_ctrl0:0x%x\n", readl(&i2s_reg->i2s_clk_ctrl0));
printf("i2s_clk_ctrl1:0x%x\n", readl(&i2s_reg->i2s_clk_ctrl1));
printf("[i2s_sys_regs][0x%p]:\n", i2s_sys_reg);
printf("i2s_tdm_sclk_in_sel:0x%x\n", i2s_sys_reg->i2s_tdm_sclk_in_sel);
printf("i2s_tdm_fs_in_sel:0x%x\n", i2s_sys_reg->i2s_tdm_fs_in_sel);
printf("i2s_tdm_sdi_in_sel:0x%x\n", i2s_sys_reg->i2s_tdm_sdi_in_sel);
printf("i2s_tdm_sdo_out_sel:0x%x\n", i2s_sys_reg->i2s_tdm_sdo_out_sel);
#endif
}
static void i2s_write_reg(volatile u32 *addr, u32 val)
{
writel(val, addr);
}
static void muteamp(bool enable)
{
debug("[%s]IN/OUT:0x%x, P/N:0x%x\n", __func__,
readl((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_INOUT)),
readl((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_PN)));
if (enable) {//0
i2s_write_reg((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_INOUT), 0);//OUT
i2s_write_reg((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_PN), 0);//DOWN
} else {//1
i2s_write_reg((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_INOUT), 4);//OUT
i2s_write_reg((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_PN), 4);//DOWN
}
debug("[%s]IN/OUT:0x%x, P/N:0x%x\n", __func__,
readl((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_INOUT)),
readl((volatile u32 *)(AMP_PWR_GPIO_BASE + AMP_PWR_GPIO_PN)));
}
void i2s_set_clk_source(struct i2s_tdm_regs *i2s_reg, unsigned int src)
{
u32 tmp = readl(&i2s_reg->i2s_clk_ctrl0) & ~(AUD_CLK_SOURCE_MASK);
switch (src) {
case AUD_CLK_FROM_MCLK_IN:
tmp |= AUD_CLK_FROM_MCLK_IN | AUD_ENABLE;
break;
case AUD_CLK_FROM_PLL:
tmp |= AUD_CLK_FROM_PLL | AUD_ENABLE;
break;
}
i2s_write_reg(&i2s_reg->i2s_clk_ctrl0, tmp);
debug("[%s]Set clk source from %d\n", __func__, src);
}
void i2s_set_interrupt(struct i2s_tdm_regs *i2s_reg)
{
i2s_write_reg(&i2s_reg->i2s_int_en, I2S_INT_EN_ALL); /* enable all interrupt mask for TX and RX */
}
void i2s_set_sample_rate(struct i2s_tdm_regs *i2s_reg, unsigned int sample_rate)
{
u32 frame_setting = 0;
u32 slot_setting = 0;
u32 data_format = 0;
u32 clk_ctrl = 0;
u32 div_multiplier = 1; /* if use audio PLL (25 or 24.576Mhz), div_multiplier should be 2 */
debug("[%s]Set sample rate to %d\n", __func__, sample_rate);
frame_setting = readl(&i2s_reg->frame_setting);
slot_setting = readl(&i2s_reg->slot_setting1);
data_format = readl(&i2s_reg->data_format);
clk_ctrl = readl(&i2s_reg->i2s_clk_ctrl1);
frame_setting &= ~(FRAME_LENGTH_MASK | FS_ACT_LENGTH_MASK);
slot_setting &= ~(SLOT_SIZE_MASK | DATA_SIZE_MASK);
data_format &= ~(WORD_LENGTH_MASK);
#if defined(CONFIG_USE_AUDIO_PLL)
clk_ctrl = MCLK_DIV(2); /* audio PLL is 25 or 24.576 Mhz, need to div with 2*/
div_multiplier = 1;
#else
clk_ctrl = MCLK_DIV(1); /* mclk_in is 12.288 Mhz, no need to div*/
#endif
switch (sample_rate) {
case 8000:
frame_setting |= FRAME_LENGTH(32) | FS_ACT_LENGTH(16);
slot_setting |= SLOT_SIZE(16) | DATA_SIZE(16);
data_format = WORD_LEN_16;
clk_ctrl |= BCLK_DIV(48 * div_multiplier);
break;
case 12000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(16 * div_multiplier);
break;
case 16000:
frame_setting |= FRAME_LENGTH(32) | FS_ACT_LENGTH(16);
slot_setting |= SLOT_SIZE(16) | DATA_SIZE(16);
data_format = WORD_LEN_16;
//clk_ctrl |= BCLK_DIV(12 * div_multiplier);
clk_ctrl |= BCLK_DIV(24 * div_multiplier);
break;
case 24000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(8 * div_multiplier);
break;
case 32000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(6 * div_multiplier);
break;
case 48000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(4 * div_multiplier);
break;
case 96000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(2 * div_multiplier);
break;
case 192000:
frame_setting |= FRAME_LENGTH(64) | FS_ACT_LENGTH(32);
slot_setting |= SLOT_SIZE(32) | DATA_SIZE(32);
data_format = WORD_LEN_32;
clk_ctrl |= BCLK_DIV(1 * div_multiplier);
break;
}
i2s_write_reg(&i2s_reg->frame_setting, frame_setting);
i2s_write_reg(&i2s_reg->slot_setting1, slot_setting);
i2s_write_reg(&i2s_reg->data_format, data_format);
i2s_write_reg(&i2s_reg->i2s_clk_ctrl1, clk_ctrl);
}
int i2s_set_fmt(struct i2s_tdm_regs *i2s_reg,
unsigned char role,
unsigned char aud_mode,
unsigned int fmt,
unsigned char slot_no)
{
unsigned int tmp = 0;
unsigned int tmp2 = 0;
//unsigned int codec_fmt = 0;
tmp = readl(&i2s_reg->frame_setting) & ~(FS_OFFSET_MASK | FS_IDEF_MASK | FS_ACT_LENGTH_MASK);
tmp2 = readl(&i2s_reg->slot_setting1) & ~(SLOT_NUM_MASK);
switch (aud_mode) {
case I2S_MODE:
tmp |= FS_OFFSET_1_BIT | FS_IDEF_I2S_LR | FS_ACT_LENGTH(((tmp & FRAME_LENGTH_MASK) + 1) / 2);
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 |= SLOT_NUM(slot_no);
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_I2S;
break;
case LJ_MODE:
tmp |= NO_FS_OFFSET | FS_IDEF_FRAME_SYNC | FS_ACT_LENGTH(((tmp & FRAME_LENGTH_MASK) + 1) / 2);
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 |= SLOT_NUM(slot_no);
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_LEFT_J;
break;
case RJ_MODE:
tmp |= (NO_FS_OFFSET | FS_IDEF_FRAME_SYNC |
FS_ACT_LENGTH(((tmp & FRAME_LENGTH_MASK) + 1) / 2));
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 &= ~(FB_OFFSET_MASK);
tmp2 |= (SLOT_NUM(slot_no) |
FB_OFFSET((((tmp & FS_ACT_LENGTH_MASK) >> 16) - ((tmp2 & DATA_SIZE_MASK) >> 16))));
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_RIGHT_J;
break;
case PCM_A_MODE:
tmp |= FS_OFFSET_1_BIT | FS_IDEF_FRAME_SYNC | FS_ACT_LENGTH(1);
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 |= SLOT_NUM(slot_no);
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_DSP_A;
break;
case PCM_B_MODE:
tmp |= NO_FS_OFFSET | FS_IDEF_FRAME_SYNC | FS_ACT_LENGTH(1);
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 |= SLOT_NUM(slot_no);
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_DSP_B;
break;
case TDM_MODE:
tmp |= NO_FS_OFFSET | FS_IDEF_FRAME_SYNC | FS_ACT_LENGTH(1);
i2s_write_reg(&i2s_reg->frame_setting, tmp);
tmp2 |= SLOT_NUM(slot_no);
i2s_write_reg(&i2s_reg->slot_setting1, tmp2);
i2s_write_reg(&i2s_reg->slot_setting2, 0x0f); /* enable slot 0-3 for TDM */
//codec_fmt |= SND_SOC_DAIFMT_PDM;
break;
default:
log_err("%s: Invalid format\n", __func__);
return -1;
}
tmp = readl(&i2s_reg->blk_mode_setting) &
~(SAMPLE_EDGE_MASK | FS_SAMPLE_RX_DELAY_MASK); /* clear bit 2~4 to set frame format */
tmp2 = readl(&i2s_reg->frame_setting) & ~(FS_POLARITY_MASK); /* clear bit 12 to set fs polarity */
if ((aud_mode == I2S_MODE) || (aud_mode == LJ_MODE) || (aud_mode == RJ_MODE)) {
switch (fmt) {
case FMT_IB_NF:
debug("Set format to IBNF\n");
#ifdef CONFIG_SHIFT_HALF_T
// if (concurrent_rx_enable == true)
// tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_P; /* for crx */
// else
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_N;
#else
tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_N;
#endif
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
tmp2 |= FS_ACT_LOW;
i2s_write_reg(&i2s_reg->frame_setting, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_IB_NF;
break;
case FMT_IB_IF:
debug("Set format to IBIF\n");
#ifdef CONFIG_SHIFT_HALF_T
//if (concurrent_rx_enable == true)
// tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_P; /* for crx */
//else
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_N;
#else
tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_N;
#endif
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
tmp2 |= FS_ACT_HIGH;
i2s_write_reg(&i2s_reg->frame_setting, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_IB_IF;
break;
case FMT_NB_NF:
debug("Set format to NBNF\n");
#ifdef CONFIG_SHIFT_HALF_T
//if (concurrent_rx_enable == true)
// tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_N; /* for crx */
//else
tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_P;
#else
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_P;
#endif
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
tmp2 |= FS_ACT_LOW;
i2s_write_reg(&i2s_reg->frame_setting, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_NB_NF;
break;
case FMT_NB_IF:
debug("Set format to NBIF\n");
#ifdef CONFIG_SHIFT_HALF_T
//if (concurrent_rx_enable == true)
// tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_N; /* for crx */
//else
tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_P;
#else
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_P;
#endif
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
tmp2 |= FS_ACT_HIGH;
i2s_write_reg(&i2s_reg->frame_setting, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_NB_IF;
break;
default:
log_err("%s: Invalid clock ploarity input\n", __func__);
return -1;
}
} else {
#ifdef CONFIG_SHIFT_HALF_T
if (role == MASTER_MODE)
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_N;
else
tmp |= RX_SAMPLE_EDGE_N | TX_SAMPLE_EDGE_N;
#else
tmp |= RX_SAMPLE_EDGE_P | TX_SAMPLE_EDGE_P;
#endif
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
tmp2 |= FS_ACT_HIGH;
i2s_write_reg(&i2s_reg->frame_setting, tmp2);
//codec_fmt |= SND_SOC_DAIFMT_IB_IF;
}
tmp=readl(&i2s_reg->blk_mode_setting) & ~(ROLE_MASK); /* clear bit 2~4 to set frame format */
switch (role) {
case MASTER_MODE:
tmp |= MASTER_MODE;
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
//i2s_set_audio_gpio(MASTER_MODE);
//codec_fmt |= SND_SOC_DAIFMT_CBS_CFS; /* Set codec to slave */
debug("master:%s\n", __func__);
break;
case SLAVE_MODE:
tmp |= SLAVE_MODE;
i2s_write_reg(&i2s_reg->blk_mode_setting, tmp);
//i2s_set_audio_gpio(SLAVE_MODE);
//codec_fmt |= SND_SOC_DAIFMT_CBM_CFM; /* Set codec to master*/
debug("slave:%s\n", __func__);
break;
default:
log_err("%s: Invalid master selection\n", __func__);
return -1;
}
// printf("Set codes fmt\n");
// if (skip_codec_setting == false)
// adau1372_set_dai_fmt(codec_fmt);
printf("[%s]end\n", __func__);
return 0;
}
void i2s_config_dma(struct i2s_tdm_regs *i2s_reg, bool on)
{
u32 blk_mode_setting = 0;
//u32 blk_cfg = 0;
blk_mode_setting = readl(&i2s_reg->blk_mode_setting) & ~(DMA_MODE_MASK);
if (on == true) {
i2s_write_reg(&i2s_reg->blk_mode_setting, blk_mode_setting | HW_DMA_MODE); /*not to use FIFO */
i2s_write_reg(&i2s_reg->fifo_threshold,
(RX_FIFO_THRESHOLD(15) | TX_FIFO_THRESHOLD(15) | TX_FIFO_HIGH_THRESHOLD(31)));
} else {
i2s_write_reg(&i2s_reg->blk_mode_setting, blk_mode_setting | SW_MODE); /*not to use FIFO */
i2s_write_reg(&i2s_reg->fifo_threshold,
(RX_FIFO_THRESHOLD(1) | TX_FIFO_THRESHOLD(15) | TX_FIFO_HIGH_THRESHOLD(31)));
}
//blk_cfg = readl(&i2s_reg->blk_cfg);
//printf("[%s]blk_cfg:0x%x\n", __func__, readl(&i2s_reg->blk_cfg));
}
static int cvitekub_i2s_init(struct i2s_uc_priv *priv)
{
int ret = 0;
struct i2s_tdm_regs *i2s_reg = (struct i2s_tdm_regs *)(uintptr_t)priv->base_address;
i2s_set_clk_source(i2s_reg, AUD_CLK_FROM_PLL);
i2s_set_interrupt(i2s_reg);
/* disable i2s transfer flag and flush the fifo */
i2s_set_sample_rate(i2s_reg, priv->samplingrate); /* sample rate must first prior to fmt */
ret = i2s_set_fmt(i2s_reg, MASTER_MODE, I2S_MODE, FMT_IB_IF, priv->channels);
if (ret != 0) {
log_err("%s:set format failed\n", __func__);
return -1;
}
i2s_config_dma(i2s_reg, false);
return 0;
}
void i2s_switch(int on, struct i2s_tdm_regs *i2s_reg)
{
u32 i2s_enable = readl(&i2s_reg->i2s_enable);
u32 aud_enable = readl(&i2s_reg->i2s_clk_ctrl0);
u32 role = (readl(&i2s_reg->blk_mode_setting) & ROLE_MASK);
if (on) {
if (i2s_enable == I2S_OFF)
i2s_write_reg(&i2s_reg->i2s_enable, I2S_ON);
} else {
if (i2s_enable == I2S_ON)
i2s_write_reg(&i2s_reg->i2s_enable, I2S_OFF);
if (((aud_enable & AUD_ENABLE) == AUD_ENABLE) && role == MASTER_MODE)
i2s_write_reg(&i2s_reg->i2s_clk_ctrl0, aud_enable & ~(AUD_ENABLE));
}
}
void i2s_txctrl(struct i2s_tdm_regs *i2s_reg, int on)
{
u32 blk_mode_setting = 0;
u32 clk_ctrl = 0;
blk_mode_setting = (readl(&i2s_reg->blk_mode_setting) & ~(TXRX_MODE_MASK));
clk_ctrl = (readl(&i2s_reg->i2s_clk_ctrl0) & ~(AUD_SWITCH));
blk_mode_setting |= TX_MODE;
i2s_write_reg(&i2s_reg->blk_mode_setting, blk_mode_setting);
debug("txctrl:%p, 0x%x\n", i2s_reg, readl(&i2s_reg->blk_mode_setting));
if ((blk_mode_setting & ROLE_MASK) == MASTER_MODE) {
if (on) {
i2s_write_reg(&i2s_reg->i2s_clk_ctrl0, clk_ctrl | AUD_ENABLE);
debug("Enable aud_en 0x%x\n", i2s_reg->i2s_clk_ctrl0);
} else {
debug("Disalbe aud_en\n");
i2s_write_reg(&i2s_reg->i2s_clk_ctrl0, clk_ctrl & ~(AUD_ENABLE));
}
} else {
i2s_write_reg(&i2s_reg->i2s_clk_ctrl0, clk_ctrl & ~(AUD_ENABLE));
}
}
void i2s_sw_reset(struct i2s_tdm_regs *i2s_reg)
{
if ((readl(&i2s_reg->blk_mode_setting) & TXRX_MODE_MASK) == TX_MODE) {
//debug("Reset i2s TX\n");
i2s_write_reg(&i2s_reg->fifo_reset, TX_FIFO_RESET_PULL_UP);
udelay(10);
i2s_write_reg(&i2s_reg->fifo_reset, TX_FIFO_RESET_PULL_DOWN);
i2s_write_reg(&i2s_reg->i2s_reset, I2S_RESET_TX_PULL_UP);
ulong start = timer_get_us() + I2S_TIMEOUT;
udelay(10);
while (1) {
printf("[debug]tx_status:%04X\n", readl(&i2s_reg->tx_status));
if ((readl(&i2s_reg->tx_status) & RESET_TX_SCLK) >> 23) {
printf("TX Reset complete\n");
break;
} else if ((long)(timer_get_us() - start) > 0) {
printf("TX Reset Timeout\n");
break;
}
}
i2s_write_reg(&i2s_reg->i2s_reset, I2S_RESET_TX_PULL_DOWN);
} else { /* reset RX*/
//debug("Reset i2s RX\n");
i2s_write_reg(&i2s_reg->fifo_reset, RX_FIFO_RESET_PULL_UP);
udelay(10);
i2s_write_reg(&i2s_reg->fifo_reset, RX_FIFO_RESET_PULL_DOWN);
i2s_write_reg(&i2s_reg->i2s_reset, I2S_RESET_RX_PULL_UP);
ulong start = timer_get_us() + I2S_TIMEOUT;
udelay(10);
while (1) {
u32 tmp = readl(&i2s_reg->rx_status);
u32 tmp2 = readl(&i2s_reg->i2s_clk_ctrl0);
printf("rx_status=0x%x, clk_ctrl0=0x%x\n", tmp, tmp2);
if ((tmp & RESET_RX_SCLK) >> 23) {
//debug("RX Reset complete\n");
break;
} else if ((long)(timer_get_us() - start) > 0) {
printf("RX Reset Timeout\n");
break;
}
}
i2s_write_reg(&i2s_reg->i2s_reset, I2S_RESET_RX_PULL_DOWN);
}
}
static int i2s_send_data(struct i2s_tdm_regs *i2s_reg, const void *byte_data, int nbytes)
{
struct i2s_sys_regs *i2s_sys_reg = (struct i2s_sys_regs *)CONFIG_SYS_I2S_SYS_BASE;
u32 *send_data = (u32 *)byte_data;
int frame_num = nbytes / 4;//2chn 16bit
int i = 0;
//u32 overrun = 0;
u32 fifo_wb = 0;
u32 fifo_depth = 16;
u32 cycle_cnt = fifo_depth;
u32 remainder = frame_num % cycle_cnt;
u32 integer = frame_num / cycle_cnt + 1;
//printf("%s fifo_depth = %d , frame_num = %d(%d)(%d), send_data = %p, i2s_reg = %p\n",
// __func__, fifo_depth, frame_num, integer, remainder, send_data, i2s_reg);
i2s_txctrl(i2s_reg, I2S_TX_ON);
i2s_sw_reset(i2s_reg);
i2s_switch(I2S_ON, i2s_reg);
muteamp(false);
while (integer) {
//overrun = readl(&i2s_reg->i2s_int);
//if (((overrun & I2S_INT_TXDA) == I2S_INT_TXDA)
//|| ((overrun & I2S_INT_TXDA_RAW) == I2S_INT_TXDA_RAW)) {
// Write 1 to clear.
// i2s_write_reg(&i2s_reg->i2s_int, overrun | I2S_INT_TXDA | I2S_INT_TXDA_RAW);
fifo_wb = readl((void *)0x0413004c) & 0x3f;
if (fifo_wb > 0xf) {
if (fifo_wb == 0x20)
printf("u\n");
if (integer > 1) {
for (i = 0; i < cycle_cnt / 2; i++) {
i2s_write_reg(&i2s_reg->tx_wr_port_ch0, *send_data);
send_data++;
i2s_write_reg(&i2s_reg->tx_wr_port_ch0, *send_data);
send_data++;
}
} else if (integer == 1) {
for (i = 0; i < remainder; i++) {
i2s_write_reg(&i2s_reg->tx_wr_port_ch0, *send_data);
send_data++;
}
}
integer--;
//udelay(10);//100(u)- 70(0)
} else if (fifo_wb == 0) {
//printf("o:%x\n", readl(&i2s_reg->i2s_int));
}
}
muteamp(true);
i2s_reg_debug(i2s_reg, i2s_sys_reg);
i2s_txctrl(i2s_reg, I2S_TX_OFF);
i2s_switch(I2S_OFF, i2s_reg);
printf("%s end\n", __func__);
return 0;
}
static int cvitekub_i2s_tx_data(struct udevice *dev, void *data, uint data_size)
{
struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
struct i2s_tdm_regs *i2s_reg = (struct i2s_tdm_regs *)(uintptr_t)priv->base_address;
return i2s_send_data(i2s_reg, data, data_size);
}
static int cvitekub_i2s_probe(struct udevice *dev)
{
struct i2s_uc_priv *priv = dev_get_uclass_priv(dev);
priv->base_address = CONFIG_SYS_I2S3_BASE;
priv->id = 1;
priv->audio_pll_clk = 24.576 * 1000 * 1000;
priv->samplingrate = 16000;
priv->bitspersample = 16;
priv->channels = 2;
priv->rfs = 64;
priv->bfs = 32;
debug("cvitekub_i2s_probe\n");
return cvitekub_i2s_init(priv);
}
static const struct i2s_ops cvitekub_i2s_ops = {
.tx_data = cvitekub_i2s_tx_data,
};
static const struct udevice_id cvitekub_i2s_ids[] = {
{ .compatible = "cvitek,cv1835-i2s" },
{ }
};
U_BOOT_DRIVER(cvitekub_i2s) = {
.name = "cvitekub_i2s",
.id = UCLASS_I2S,
.of_match = cvitekub_i2s_ids,
.probe = cvitekub_i2s_probe,
.ops = &cvitekub_i2s_ops,
//.priv_auto = sizeof(struct broadwell_i2s_priv),
};
u-boot-2021.10/drivers/cvi_sound/cvi-i2s.h 0 → 100644
View file @ 1f388afc
/*
* Copyright (C) 2023 bitmain
*/
#ifndef __CVI_I2S_H_
#define __CVI_I2S_H_
#define I2S0 0
#define I2S1 1
#define I2S2 2
#define I2S3 3
#define CONFIG_SYS_I2S0_BASE 0x04100000
#define CONFIG_SYS_I2S1_BASE 0x04110000
#define CONFIG_SYS_I2S2_BASE 0x04120000
#define CONFIG_SYS_I2S3_BASE 0x04130000
#define CONFIG_SYS_I2S_SYS_BASE 0x04108000
#define REG_AUDIO_SRC_BASE 0x041D0000
#define REG_AUDIO_MISC_BASE 0x041D0C00
#define REG_AUDIO_GPIO_BASE 0x0300A12C
#define CONFIG_USE_AUDIO_PLL
#define CONFIG_SHIFT_HALF_T
//shit 1/2 T for inv, ex master generate data at falling edge and let codec sample at rising edge//
#define I2S_BITS_PER_LONG 32
#define BIT(nr) (1UL << (nr))
#define I2S_GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (I2S_BITS_PER_LONG - 1 - (h))))
struct i2s_tdm_regs {
u32 blk_mode_setting; /* 0x00 */
u32 frame_setting; /* 0x04 */
u32 slot_setting1; /* 0x08 */
u32 slot_setting2; /* 0x0c */
u32 data_format; /* 0x10 */
u32 blk_cfg; /* 0x14 */
u32 i2s_enable; /* 0x18 */
u32 i2s_reset; /* 0x1C */
u32 i2s_int_en; /* 0x20 */
u32 i2s_int; /* 0x24 */
u32 fifo_threshold; /* 0x28 */
u32 dummy1[1]; /* 0x2c */
u32 fifo_reset; /* 0x30 */
u32 dummy2[3]; /* 0x34 ~ 0x3C */
u32 rx_status; /* 0x40 */
u32 dummy3[1]; /* 0x44 */
u32 tx_status; /* 0x48 */
u32 dummy4[5]; /* 0x4c ~ 0x5c */
u32 i2s_clk_ctrl0; /* 0x60 */
u32 i2s_clk_ctrl1; /* 0x64 */
u32 dummy5[6]; /* 0x68 ~ 0x7c */
u32 rx_rd_port_ch0; /* 0x80 */
u32 rx_rd_port_ch1; /* 0x84 */
u32 dummy6[14]; /* 0x88 ~ 0xbc */
u32 tx_wr_port_ch0; /* 0xc0 */
u32 tx_wr_port_ch1; /* 0xc4 */
};
struct i2s_sys_regs {
u32 i2s_tdm_sclk_in_sel; /* 0x000 */
u32 i2s_tdm_fs_in_sel; /* 0x004 */
u32 i2s_tdm_sdi_in_sel; /* 0x008 */
u32 i2s_tdm_sdo_out_sel; /* 0x00C */
u32 dummy1[4];
u32 i2s_tdm_multi_sync; /* 0x020 */
u32 dummy2[3];
u32 i2s_bclk_oen_sel; /* 0x030 */
u32 i2s_bclk_out_ctrl; /* 0x034 */
u32 dummy3[2];
u32 audio_pdm_ctrl; /* 0x040 */
u32 dummy4[3];
u32 audio_phy_bypass1; /* 0x050 */
u32 audio_phy_bypass2; /* 0x054 */
u32 dummy5[6];
u32 i2s_sys_clk_ctrl; /* 0x070 */
u32 dummy6[3];
u32 i2s0_master_clk_ctrl0; /* 0x080 */
u32 i2s0_master_clk_ctrl1; /* 0x084 */
u32 dummy7[2];
u32 i2s1_master_clk_ctrl0; /* 0x090 */
u32 i2s1_master_clk_ctrl1; /* 0x094 */
u32 dummy8[2];
u32 i2s2_master_clk_ctrl0; /* 0x0A0 */
u32 i2s2_master_clk_ctrl1; /* 0x0A4 */
u32 dummy9[2];
u32 i2s3_master_clk_ctrl0; /* 0x0B0 */
u32 i2s3_master_clk_ctrl1; /* 0x0B4 */
u32 dummy10[2];
u32 i2s_sys_lrck_ctrl; /* 0x0C0 */
};
struct reg_audio_misc_regs {
u32 dummy[12];
u32 reg_pdm_en; /* 0x30 */
u32 reg_pdm_clk; /* 0x34 */
u32 reg_pdm_i2s; /* 0x38 */
};
struct reg_audio_src_regs {
u32 reg_src_en; /* 0x00 */
u32 reg_src_sel; /* 0x04 */
u32 reg_src_setting; /* 0x08 */
u32 reg_src_format; /* 0x0c */
u32 dummy1[5];
u32 reg_src_ratio; /* 0x24 */
u32 reg_src_fsi_init; /* 0x28 */
u32 dummy2[1];
u32 reg_src_i2s_status; /* 0x30 */
u32 dummy3[11];
u32 reg_src_data_out; /* 0x60 */
u32 reg_dma_th; /* 0x64 */
};
#define I2S_TIMEOUT 2000000
#define I2S_MODE 0x0
#define LJ_MODE 0x1
#define RJ_MODE 0x2
#define PCM_A_MODE 0x3
#define PCM_B_MODE 0x4
#define TDM_MODE 0x5
/* define value of each configuration of register BLK_MODE_SETTING */
#define RX_MODE 0x0 << 0
#define TX_MODE 0x1 << 0
#define SLAVE_MODE 0x0 << 1
#define MASTER_MODE 0x1 << 1
#define RX_SAMPLE_EDGE_N 0x0 << 2 /* Negative edge */
#define RX_SAMPLE_EDGE_P 0x1 << 2 /* Positive edge */
#define TX_SAMPLE_EDGE_N 0x0 << 3
#define TX_SAMPLE_EDGE_P 0x1 << 3
#define FS_SAMPLE_EDGE_N 0x0 << 4
#define FS_SAMPLE_EDGE_P 0x1 << 4
#define FS_SAMPLE_RX_DELAY 0x1 << 5
#define FS_SAMPLE_RX_NO_DELAY 0x0 << 5
#define SW_MODE 0x0 << 7
#define HW_DMA_MODE 0x1 << 7
#define MULTI_I2S_SYNC 0x1 << 8
#define TXRX_MODE_MASK 0x00000001
#define ROLE_MASK 0x00000002
#define SAMPLE_EDGE_MASK 0x0000001C
#define FS_SAMPLE_RX_DELAY_MASK 0x00000020
#define DMA_MODE_MASK 0x00000080
#define MULTI_I2S_MODE_MASK 0x00000100
/* define value of each configuration of register FRAME_SETTING */
#define FS_POLARITY_MASK 0x00001000
#define FS_OFFSET_MASK 0x00002000
#define FS_IDEF_MASK 0x00004000
#define FS_ACT_LENGTH_MASK 0x00FF0000
#define FRAME_LENGTH_MASK 0x000001FF
#define FRAME_LENGTH(l) (((l-1) << 0) & FRAME_LENGTH_MASK) /* frame length between 0~511 = 1~512 bits */
#define FS_ACT_LOW 0x0 << 12
#define FS_ACT_HIGH 0x1 << 12
#define NO_FS_OFFSET 0x0 << 13
#define FS_OFFSET_1_BIT 0x1 << 13
#define FS_IDEF_FRAME_SYNC 0x0 << 14 /* frame sync*/
#define FS_IDEF_I2S_LR 0x1 << 14 /* frame sync*/
#define FS_IDEF_CH_SYNC 0x1 << 14 /* channel sync */
#define FS_ACT_LENGTH(l) (((l-1) << 16) & FS_ACT_LENGTH_MASK) /* frame active length between 0~255 = 1~256 bits*/
/* define value of each configuration of register SLOT_SETTING1 */
#define SLOT_NUM_MASK 0x0000000F
#define SLOT_SIZE_MASK 0x00003F00
#define DATA_SIZE_MASK 0x001F0000
#define FB_OFFSET_MASK 0x1F000000
#define SLOT_NUM(l) (((l-1) << 0) & SLOT_NUM_MASK)
#define SLOT_SIZE(l) (((l-1) << 8) & SLOT_SIZE_MASK)
#define DATA_SIZE(l) (((l-1) << 16) & DATA_SIZE_MASK)
#define FB_OFFSET(l) ((l << 24) & FB_OFFSET_MASK)
/* define value of each configuration of register DATA_FORMAT */
#define WORD_LENGTH_MASK 0x00000006
#define WORD_LEN_8 0x0 << 1
#define WORD_LEN_16 0x1 << 1
#define WORD_LEN_32 0x2 << 1
/* define value of each configuration of register BLK_CFG */
#define AUTO_DISABLE_W_CH_EN 0x1 << 4
#define RX_START_WAIT_DMA_EN 0x1 << 6
/* define value of each configuration of register I2S_RESET */
#define I2S_RESET_RX_PULL_UP 0x00000001
#define I2S_RESET_RX_PULL_DOWN 0x00000000
#define I2S_RESET_TX_PULL_UP 0x00000002
#define I2S_RESET_TX_PULL_DOWN 0x00000000
/* define value of each configuration of register I2S_INT_EN */
#define I2S_INT_EN_ALL 0x00000177
/* define value of each configuration of register I2S_INT */
#define I2S_INT_RXDA 0x1 << 0 /* RX FIFO data available interrupt status */
#define I2S_INT_RXFO 0x1 << 1 /* RX FIFO overflow interrupt status */
#define I2S_INT_RXFU 0x1 << 2 /* RX FIFO underflow interrupt status */
#define I2S_INT_TXDA 0x1 << 4 /* RX FIFO data available interrupt status */
#define I2S_INT_TXFO 0x1 << 5 /* RX FIFO overflow interrupt status */
#define I2S_INT_TXFU 0x1 << 6 /* RX FIFO underflow interrupt status */
#define I2S_INT_RXDA_RAW 0x1 << 8 /* RX FIFO data available interrupt raw status */
#define I2S_INT_RXFO_RAW 0x1 << 9 /* RX FIFO overflow interrupt raw status */
#define I2S_INT_RXFU_RAW 0x1 << 10 /* RX FIFO underflow interrupt raw status */
#define I2S_INT_TXDA_RAW 0x1 << 12 /* RX FIFO data available interrupt raw status */
#define I2S_INT_TXFO_RAW 0x1 << 13 /* RX FIFO overflow interrupt raw status */
#define I2S_INT_TXFU_RAW 0x1 << 14 /* RX FIFO underflow interrupt raw status */
/* define value of each configuration of register FIFO_THRESHOLD */
#define RX_FIFO_THRESHOLD_MASK 0x0000001F
#define TX_FIFO_THRESHOLD_MASK 0x001F0000
#define TX_FIFO_HIGH_THRESHOLD_MASK 0x1F000000
#define RX_FIFO_THRESHOLD(v) ((v << 0) & RX_FIFO_THRESHOLD_MASK)
#define TX_FIFO_THRESHOLD(v) ((v << 16) & TX_FIFO_THRESHOLD_MASK)
#define TX_FIFO_HIGH_THRESHOLD(v) ((v << 24) & TX_FIFO_HIGH_THRESHOLD_MASK)
/* define value of each configuration of register FIFO_RESET */
#define RX_FIFO_RESET_PULL_UP 0x00000001
#define RX_FIFO_RESET_PULL_DOWN 0x00000000
#define TX_FIFO_RESET_PULL_UP 0x00010000
#define TX_FIFO_RESET_PULL_DOWN 0x00000000
/* define value of each configuration of register RX_STATUS */
#define RESET_RX_SCLK 0x00800000
/* define value of each configuration of register TX_STATUS */
#define RESET_TX_SCLK 0x00800000
/* define value of each configuration of register CLK_CTRL0 */
#define AUD_CLK_SOURCE_MASK 0x00000001
#define AUD_SWITCH 0x00000100
#define AUD_CLK_FROM_PLL 0x0 << 0
#define AUD_CLK_FROM_MCLK_IN 0x1 << 0
#define ADU_BCLK_OUT_EN 0x1 << 6
#define AUD_MCLK_OUT_EN 0x1 << 7
#define AUD_DISABLE 0x0 << 8
#define AUD_ENABLE 0x1 << 8
/* define value of each configuration of register CLK_CTRL1 */
#define MCLK_DIV(l) ((l << 0) & 0x0000FFFF)
#define BCLK_DIV(l) ((l << 16) & 0xFFFF0000)
#define FMT_IB_NF 0 /* sample at falling edge and sync polarity is active low*/
#define FMT_IB_IF 1
#define FMT_NB_NF 2
#define FMT_NB_IF 3
#define I2S_ON 1
#define I2S_OFF 0
/* I2S Tx Control */
#define I2S_TX_ON 1
#define I2S_TX_OFF 0
/* I2S Rx Control */
#define I2S_RX_ON 1
#define I2S_RX_OFF 0
#define WSS_16_CLKCYCLE 0x20
#define WSS_24_CLKCYCLE 0x30
#define WSS_32_CLKCYCLE 0x40
#define WSS_256_CLKCYCLE 0x200
#define AUD_SRC_EN 0x1 << 0
#define AUD_SRC_OFF 0x0 << 0
#define AUD_SRC_FSI(v) ((v << 0) & 0x000003FF)
#define AUD_SRC_FSO(v) ((v << 16) & 0x03FF0000)
/* This structure stores the i2s related information */
struct i2stx_info {
unsigned int rfs; /* LR clock frame size */
unsigned int sclkg; /* sclk gate */
/* unsigned int audio_pll_clk;*/ /* Audio pll frequency in Hz */
unsigned int samplingrate; /* sampling rate */
unsigned int mclk_out_en;
unsigned int clk_src;
unsigned int bitspersample; /* bits per sample */
unsigned int channels; /* audio channels */
struct i2s_tdm_regs *base_address; /* I2S Register Base */
struct i2s_sys_regs *sys_base_address;
unsigned int id; /* I2S controller id */
unsigned char role; /* Master mode or slave mode*/
unsigned char slot_no;
unsigned int inv; /* Normal or invert BCLK, normal or invert WS CLK (FSYNC)*/
unsigned char aud_mode; /*I2S mode, Left justified mode or Right justified mode*/
u16 mclk_div;
u16 bclk_div;
u16 sync_div;
};
struct i2s_tdm_regs *i2s_get_base(unsigned int i2s_no);
struct i2s_sys_regs *i2s_get_sys_base(void);
// void i2s_set_clk_source(struct i2s_tdm_regs *i2s_reg, unsigned int src);
// void i2s_set_mclk_out_enable(struct i2s_tdm_regs *i2s_reg, unsigned int enable);
// void i2s_set_sample_rate(struct i2s_tdm_regs *i2s_reg, unsigned int sample_rate);
// void i2s_set_ws_clock_cycle(struct i2s_tdm_regs *i2s_reg, unsigned int ws_clk, u8 aud_mode);
// void i2s_set_resolution(struct i2s_tdm_regs *i2s_reg, unsigned int data_size, unsigned int slot_size);
// int i2s_set_fmt(struct i2s_tdm_regs *i2s_reg,
// unsigned char role,
// unsigned char aud_mode,
// unsigned int fmt,
// unsigned char slot_no);
// int i2s_init(struct i2stx_info *pi2s_tx, unsigned int *data);
// void i2s_loop_test(struct i2stx_info *pi2s_tx, unsigned int sec, unsigned int *data);
// void i2s_pdm_loop_test(struct i2stx_info *pi2s_tx, unsigned int sec, unsigned int *data);
// void i2s_src_test(struct i2stx_info *pi2s_tx);
// int i2s_test_rx(struct i2stx_info *pi2s_tx, unsigned int resolution);
// int i2s_receive_rx_data(struct i2stx_info *pi2s_tx, unsigned int *data);
// int i2s_transfer_tx_data(struct i2stx_info *pi2s_tx, unsigned int *data, unsigned long data_size);
// void concurrent_rx(void);
#endif /* __CVI_I2S_H_ */
u-boot-2021.10/drivers/cvi_sound/cvi-sound-uclass.c 0 → 100644
View file @ 1f388afc
#include <dm/uclass.h>
#include <sound.h>
UCLASS_DRIVER(sound) = {
.id = UCLASS_SOUND,
.name = "sound",
.per_device_auto = sizeof(struct sound_uc_priv),
};
u-boot-2021.10/drivers/cvi_sound/cvi-sound.c 0 → 100644
View file @ 1f388afc
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2023 bitmain
*/
#include <common.h>
#include <linux/types.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <audio_codec.h>
#include <sound.h>
#include <dm.h>
#include <i2s.h>
#include <log.h>
#include <sound.h>
static int cvitekub_sound_setup(struct udevice *dev)
{
struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
struct i2s_uc_priv *i2c_priv = dev_get_uclass_priv(uc_priv->i2s);
int ret = 0;
if (uc_priv->setup_done) {
printf("areadly init\n");
return ret;
}
ret = audio_codec_set_params(uc_priv->codec, i2c_priv->id,
i2c_priv->samplingrate,
i2c_priv->samplingrate * i2c_priv->rfs,
i2c_priv->bitspersample,
i2c_priv->channels);
if (ret)
return ret;
uc_priv->setup_done = true;
return 0;
}
static int cvitekub_sound_play(struct udevice *dev, void *data, uint data_size)
{
struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
return i2s_tx_data(uc_priv->i2s, data, data_size);
}
static int cvitekub_sound_stop_play(struct udevice *dev)
{
struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
audio_codec_close(uc_priv->codec); //because of pop
uc_priv->setup_done = false;
return 0;
}
static int cvitekub_sound_probe(struct udevice *dev)
{
printf("cvitekub_sound_probe\n");
int ret = 0;
struct sound_uc_priv *uc_priv = dev_get_uclass_priv(dev);
ret = uclass_get_device_by_driver(UCLASS_AUDIO_CODEC, DM_DRIVER_GET(cvitekub_dac),
&uc_priv->codec);
if (ret) {
printf("[error][%s]no cvitekub_dac device ret:%d\n", __func__, ret);
return -1;
}
ret = uclass_get_device_by_name(UCLASS_I2S, "i2s@04130000",
&uc_priv->i2s);
if (ret) {
printf("[error][%s]no cvitekub_i2s device ret:%d\n", __func__, ret);
return -1;
}
printf("Probed sound '%s' with codec '%s' and i2s '%s'\n", dev->name,
uc_priv->codec->name, uc_priv->i2s->name);
return 0;
}
static const struct sound_ops cvitekub_sound_ops = {
.setup = cvitekub_sound_setup,
.play = cvitekub_sound_play,
.stop_play = cvitekub_sound_stop_play,
};
static const struct udevice_id cvitekub_sound_ids[] = {
{ .compatible = "cvitek,cv182xa-dac" },
{ }
};
U_BOOT_DRIVER(cvitekub_sound) = {
.name = "cvitekub_sound",
.id = UCLASS_SOUND,
.of_match = cvitekub_sound_ids,
.probe = cvitekub_sound_probe,
.ops = &cvitekub_sound_ops,
};
u-boot-2021.10/drivers/cvi_sound/cvi-src.h 0 → 100644
View file @ 1f388afc
This source diff could not be displayed because it is too large. You can view the blob instead.
u-boot-2021.10/drivers/mmc/Makefile
View file @ 1f388afc
......@@ -83,4 +83,5 @@ obj-$(CONFIG_TARGET_CVITEK_CV1835) += cvitek/sdhci-cv183x.o
obj-$(CONFIG_TARGET_CVITEK_CV1822) += cvitek/sdhci-cv182x.o
obj-$(CONFIG_TARGET_CVITEK_CV181X) += cvitek/sdhci-cv181x.o
obj-$(CONFIG_TARGET_CVITEK_CV180X) += cvitek/sdhci-cv180x.o
obj-$(CONFIG_TARGET_CVITEK_ATHENA2) += cvitek/sdhci-athena2.o
endif
u-boot-2021.10/drivers/net/phy/cvitek.c
View file @ 1f388afc
......@@ -134,26 +134,27 @@ static void cv182xa_ephy_init(void)
// En TX_Rterm
mmio_write_32(0x03009040, (0x0001 | mmio_read_32(0x03009040)));
// change rx vcm
mmio_write_32(0x0300904c, (0x820 | mmio_read_32(0x0300904c)));
// Link Pulse
// Switch to MII-page10
mmio_write_32(0x0300907c, 0x0a00);
#if 1
// Set Link Pulse
// mmio_write_32(0x03009040, 0x3e00);
// mmio_write_32(0x03009044, 0x7864);
// mmio_write_32(0x03009048, 0x6470);
// mmio_write_32(0x0300904c, 0x5f62);
// mmio_write_32(0x03009050, 0x5a5a);
// mmio_write_32(0x03009054, 0x5458);
// mmio_write_32(0x03009058, 0xb23a);
// mmio_write_32(0x0300905c, 0x94a0);
// mmio_write_32(0x03009060, 0x9092);
// mmio_write_32(0x03009064, 0x8a8e);
// mmio_write_32(0x03009068, 0x8688);
// mmio_write_32(0x0300906c, 0x8484);
// mmio_write_32(0x03009070, 0x0082);
mmio_write_32(0x03009040, 0x3e00);
mmio_write_32(0x03009044, 0x7864);
mmio_write_32(0x03009048, 0x6470);
mmio_write_32(0x0300904c, 0x5f62);
mmio_write_32(0x03009050, 0x5a5a);
mmio_write_32(0x03009054, 0x5458);
mmio_write_32(0x03009058, 0xb23a);
mmio_write_32(0x0300905c, 0x94a0);
mmio_write_32(0x03009060, 0x9092);
mmio_write_32(0x03009064, 0x8a8e);
mmio_write_32(0x03009068, 0x8688);
mmio_write_32(0x0300906c, 0x8484);
mmio_write_32(0x03009070, 0x0082);
#else
// from sean
// Fix err: the status is still linkup when removed the network cable.
mmio_write_32(0x03009040, 0x2000);
......@@ -169,7 +170,7 @@ static void cv182xa_ephy_init(void)
mmio_write_32(0x03009068, 0x8283);
mmio_write_32(0x0300906c, 0x8182);
mmio_write_32(0x03009070, 0x0081);
#endif
// TP_IDLE
// Switch to MII-page11
mmio_write_32(0x0300907c, 0x0b00);
......
u-boot-2021.10/include/audio_codec.h
View file @ 1f388afc
......@@ -29,6 +29,8 @@ struct audio_codec_ops {
*/
int (*set_params)(struct udevice *dev, int interface, int rate,
int mclk_freq, int bits_per_sample, uint channels);
int (*codec_close)(struct udevice *dev);
};
#define audio_codec_get_ops(dev) ((struct audio_codec_ops *)(dev)->driver->ops)
......@@ -47,4 +49,6 @@ struct audio_codec_ops {
int audio_codec_set_params(struct udevice *dev, int interface, int rate,
int mclk_freq, int bits_per_sample, uint channels);
int audio_codec_close(struct udevice *dev);
#endif /* __AUDIO_CODEC_H__ */
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