- 25 Apr, 2022 3 commits
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
Using all the work from @hfellner and others, add FreeRTOS SMP support. Allow idling cores through the FreeRTOS FIFO queue to allow for file system and EEPROM support. Make delay a weak function so FreeRTOS can override. Add cycle count support under FreeRTOS using a PIO SM. Use a task-based approach for handling the USB periodic work instead of the IRQ-based one in the main core. Set 8 prio levels so it fits in 3 bits nicely (0..7).
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- 24 Apr, 2022 3 commits
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Earle F. Philhower, III authored
I receive mails weekly asking how to use `SoftwareSerial` on this core. Avoid the issue by including a simple wrapper class around `SerialPIO` which gives the proper class name and constructor parameters. Note that inverted mode is not supported.
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Earle F. Philhower, III authored
Matching the Arduino SoftwareSerial API
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Earle F. Philhower, III authored
Fixes #522
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- 22 Apr, 2022 3 commits
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
Adjust the 1/2 bit time to match the number of extra cycles in the actual PIO loop. Throw out the entire start bit, which results in sampling the data at the midpoint and not the starting time of a bit (which was causing random failures on read data). Tested at 300bps all the way to 2,000,000bps using a loopback connection. Fixes #360
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- 17 Apr, 2022 2 commits
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
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- 16 Apr, 2022 1 commit
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Earle F. Philhower, III authored
Fixes #537
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- 10 Apr, 2022 1 commit
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Jean-Luc Béchennec authored
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- 09 Apr, 2022 1 commit
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Earle F. Philhower, III authored
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- 30 Mar, 2022 1 commit
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Earle F. Philhower, III authored
Fixes #524
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- 29 Mar, 2022 1 commit
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Arya11111 authored
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- 17 Mar, 2022 1 commit
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Earle F. Philhower, III authored
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- 16 Mar, 2022 2 commits
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randomllama authored
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Earle F. Philhower, III authored
* Avoid "chunkiness" of UART FIFO availability The UART FIFO will generate an IRQ to transfer data into the SerialUART FIFOs either every 4 received bytes, or every 4 idle byte times. This causes the ::available count to report "0" until either of those two cases happen, causing a potentially delay in data becoming available to the app. Change the code to pull data from the HW FIFO on a read/available/peek. Use a non-blocking mutex and IRQ disabling to safely empty the FIFO from user space. The mutex added to the IRQ is non-blocking and will be a single CAS the vast majority of the time, so it should not impact the Serial performance. Fixes #464 and others where `setPollingMode()` was needed as a workaround. Make sure we have all mutexes locked before we disable the port and free the queue to avoid evil cases. Only init the mutexes once, on object creation. In polled mode, don't bother acquiring/releasing the fifo mutex. When begin() is called on an already running port, call end() to clean up the old data/etc. before making a new queue/config. This avoids a memory leak and potential write-after-free case.
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- 14 Mar, 2022 1 commit
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- 06 Mar, 2022 1 commit
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Earle F. Philhower, III authored
Define ARDUINO_PICO_MAJOR/_MINOR/_REVISION for app use and update the Platform.IO and Arduino files for a new release version. Fixes #309 Fixes #487
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- 05 Mar, 2022 1 commit
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Earle F. Philhower, III authored
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- 24 Feb, 2022 3 commits
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
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Arya11111 authored
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- 23 Feb, 2022 2 commits
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Earle F. Philhower, III authored
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- 22 Feb, 2022 1 commit
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Pontus Oldberg authored
* Added missing SERIAL2 and LoRa module GIO pins. * Added support for enabling UART CTS and RTS pins.
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- 20 Feb, 2022 4 commits
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Bodmer authored
The PIO and state machine were hard wired, so this caused problems if they were not free. The approach used by the Servo library has been adopted so a free PIO and SM are searched. The DMA_IRQ_0 was grabbed exclusively, but this conflicts with SPI DMA use. The interrupt is now shared, but has been allocated the highest possible priority. Since the PDM PIO use is receive only, the PIO state machine RX FIFO's can be joined to reduce DMA interrupt load.
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Earle F. Philhower, III authored
Reorder the boards menu to make it easier to find any specific board. Add a note to the script asking manufacturers to keep it that way.
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Earle F. Philhower, III authored
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Magnus Nordlander authored
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- 19 Feb, 2022 2 commits
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Earle F. Philhower, III authored
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Pontus Oldberg authored
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- 15 Feb, 2022 1 commit
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Earle F. Philhower, III authored
Fixes #489 Only the PIO0 IRQ handler was ever installed due to a hardcoding bug. Attach the IRQ handler to the PIO being started instead.
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- 13 Feb, 2022 1 commit
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Earle F. Philhower, III authored
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- 12 Feb, 2022 2 commits
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Earle F. Philhower, III authored
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Earle F. Philhower, III authored
GDB for non-Linux systems was built w/o expat which caused odd behavior under Windows and other systems (i.e. breakpoints not working, etc.) New toolchain manually builds cross-compiled libexpat and ensures it is used, fixing the issue. Windows OpenOCD binaries now come from manually built and tested copies (using a real Windows system). Fixes #478 Fixes #457 Fixes #456 and probably others...
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- 10 Feb, 2022 2 commits
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Earle F. Philhower, III authored
Fixes #472 Instead of using interrupts, explicitly call the IRQ handler dueing Serial read/peek/available calls. Add to keywords.txt for syntax hilighting. Add poll calls in the SerialUART::write-like calls (write, flush, etc.) Really remove division from IRQ routines/
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Earle F. Philhower, III authored
Microsoft is deprecating WMIC, so fall back to a Powershell call in case of failure to ruin WMIC. Belt and suspenders, set PowerShell non-interactive mode and null STDIN.
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