Commit c43814bb authored by corcrash's avatar corcrash Committed by GitHub

Merge pull request #247 from corcrash/master

Added support for boards using SPIDEV with GPIO identifiers higher than 255
parents 575183c3 3c4f8420
...@@ -415,7 +415,7 @@ void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) ...@@ -415,7 +415,7 @@ void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty)
#endif #endif
/****************************************************************************/ /****************************************************************************/
RF24::RF24(uint8_t _cepin, uint8_t _cspin): RF24::RF24(uint16_t _cepin, uint16_t _cspin):
ce_pin(_cepin), csn_pin(_cspin), p_variant(false), ce_pin(_cepin), csn_pin(_cspin), p_variant(false),
payload_size(32), dynamic_payloads_enabled(false), addr_width(5),csDelay(5)//,pipe0_reading_address(0) payload_size(32), dynamic_payloads_enabled(false), addr_width(5),csDelay(5)//,pipe0_reading_address(0)
{ {
...@@ -425,8 +425,9 @@ RF24::RF24(uint8_t _cepin, uint8_t _cspin): ...@@ -425,8 +425,9 @@ RF24::RF24(uint8_t _cepin, uint8_t _cspin):
/****************************************************************************/ /****************************************************************************/
#if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor #if defined (RF24_LINUX) && !defined (MRAA)//RPi constructor
RF24::RF24(uint8_t _cepin, uint8_t _cspin, uint32_t _spi_speed):
ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5),csDelay(5)//,pipe0_reading_address(0) RF24::RF24(uint16_t _cepin, uint16_t _cspin, uint32_t _spi_speed):
ce_pin(_cepin),csn_pin(_cspin),spi_speed(_spi_speed),p_variant(false), payload_size(32), dynamic_payloads_enabled(false),addr_width(5)//,pipe0_reading_address(0)
{ {
pipe0_reading_address[0]=0; pipe0_reading_address[0]=0;
} }
......
...@@ -64,8 +64,8 @@ private: ...@@ -64,8 +64,8 @@ private:
GPIO gpio; GPIO gpio;
#endif #endif
uint8_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */ uint16_t ce_pin; /**< "Chip Enable" pin, activates the RX or TX role */
uint8_t csn_pin; /**< SPI Chip select */ uint16_t csn_pin; /**< SPI Chip select */
uint16_t spi_speed; /**< SPI Bus Speed */ uint16_t spi_speed; /**< SPI Bus Speed */
#if defined (RF24_LINUX) || defined (XMEGA_D3) #if defined (RF24_LINUX) || defined (XMEGA_D3)
uint8_t spi_rxbuff[32+1] ; //SPI receive buffer (payload max 32 bytes) uint8_t spi_rxbuff[32+1] ; //SPI receive buffer (payload max 32 bytes)
...@@ -107,7 +107,7 @@ public: ...@@ -107,7 +107,7 @@ public:
* @param _cepin The pin attached to Chip Enable on the RF module * @param _cepin The pin attached to Chip Enable on the RF module
* @param _cspin The pin attached to Chip Select * @param _cspin The pin attached to Chip Select
*/ */
RF24(uint8_t _cepin, uint8_t _cspin); RF24(uint16_t _cepin, uint16_t _cspin);
//#if defined (RF24_LINUX) //#if defined (RF24_LINUX)
/** /**
...@@ -121,7 +121,7 @@ public: ...@@ -121,7 +121,7 @@ public:
* @param spispeed For RPi, the SPI speed in MHZ ie: BCM2835_SPI_SPEED_8MHZ * @param spispeed For RPi, the SPI speed in MHZ ie: BCM2835_SPI_SPEED_8MHZ
*/ */
RF24(uint8_t _cepin, uint8_t _cspin, uint32_t spispeed ); RF24(uint16_t _cepin, uint16_t _cspin, uint32_t spispeed );
//#endif //#endif
#if defined (RF24_LINUX) #if defined (RF24_LINUX)
...@@ -1981,4 +1981,3 @@ private: ...@@ -1981,4 +1981,3 @@ private:
*/ */
#endif // __RF24_H__ #endif // __RF24_H__
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