Merge remote-tracking branch 'origin/Updates'

RF24.cpp

@@ -26,7 +26,22 @@ void RF24::csn(bool mode)
 	#endif
 #endif
 
-#if !defined  (__arm__) || defined (CORE_TEENSY)
+
+#if defined (RF24_TINY)
+	if (ce_pin != csn_pin) {
+		digitalWrite(csn_pin,mode);
+	} 
+	else {
+		if (mode == HIGH) {
+			PORTB |= (1<<PINB2);  	// SCK->CSN HIGH
+			delayMicroseconds(100); // allow csn to settle.
+		} 
+		else {
+			PORTB &= ~(1<<PINB2);	// SCK->CSN LOW
+			delayMicroseconds(20);  // allow csn to settle
+		}
+	}		
+#else if !defined  (__arm__) || defined (CORE_TEENSY)
 	digitalWrite(csn_pin,mode);		
 #endif
 
@@ -36,7 +51,8 @@ void RF24::csn(bool mode)
 
 void RF24::ce(bool level)
 {
-  digitalWrite(ce_pin,level);
+  //Allow for 3-pin use on ATTiny
+  if (ce_pin != csn_pin) digitalWrite(ce_pin,level);
 }
 
 /****************************************************************************/
@@ -420,6 +436,7 @@ void RF24::printDetails(void)
   printf_P(PSTR("CRC Length\t = %S\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()]));
   printf_P(PSTR("PA Power\t = %S\r\n"),pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()]));
 #endif
+
 }
 
 #endif
@@ -428,7 +445,7 @@ void RF24::printDetails(void)
 void RF24::begin(void)
 {
   // Initialize pins
-  pinMode(ce_pin,OUTPUT);
+  if (ce_pin != csn_pin) pinMode(ce_pin,OUTPUT);
 
   #if defined(__arm__) && ! defined( CORE_TEENSY )
   	SPI.begin(csn_pin);					// Using the extended SPI features of the DUE
@@ -438,7 +455,7 @@ void RF24::begin(void)
 	ce(LOW);
   	//csn(HIGH);
   #else
-    pinMode(csn_pin,OUTPUT);
+    if (ce_pin != csn_pin) pinMode(csn_pin,OUTPUT);
     SPI.begin();
     ce(LOW);
   	csn(HIGH);
@@ -504,7 +521,9 @@ void RF24::begin(void)
 
 void RF24::startListening(void)
 {
+ #if !defined (RF24_TINY)
   powerUp();
+ #endif
   write_register(CONFIG, read_register(CONFIG) | _BV(PRIM_RX));
   write_register(STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) );
 
@@ -545,6 +564,14 @@ void RF24::stopListening(void)
   }
   //flush_rx();
   write_register(CONFIG, ( read_register(CONFIG) ) & ~_BV(PRIM_RX) );
+ 
+  #if defined (RF24_TINY)
+  // for 3 pins solution TX mode is only left with additonal powerDown/powerUp cycle
+  if (ce_pin == csn_pin) {
+    powerDown();
+	powerUp();
+  }
+  #endif
   write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0
   
   delayMicroseconds(100);

examples/rf24ping85/rf24ping85.ino → examples/rf24_ATTiny/rf24ping85/rf24ping85.ino

@@ -10,21 +10,50 @@ version 2 as published by the Free Software Foundation.
     The ATtiny85 will transmit a counting number every second starting from 1.
     The ATtiny85 uses the tiny-core by CodingBadly (https://code.google.com/p/arduino-tiny/)
     When direct use of 3v3 does not work (UNO boards have bad 3v3 line) use 5v with LED (1.8V ~ 2.2V drop)
-
+    For low power consumption solutions floating pins (SCK and MOSI) should be pulled high or low with eg. 10K
 
     ** Hardware configuration **
-    ATtiny25/45/85 Pin map
+    ATtiny25/45/85 Pin map with CE_PIN 3 and CSN_PIN 4
+                                 +-\/-+
+                   NC      PB5  1|o   |8  Vcc --- nRF24L01  VCC, pin2 --- LED --- 5V
+    nRF24L01  CE, pin3 --- PB3  2|    |7  PB2 --- nRF24L01  SCK, pin5
+    nRF24L01 CSN, pin4 --- PB4  3|    |6  PB1 --- nRF24L01 MOSI, pin7
+    nRF24L01 GND, pin1 --- GND  4|    |5  PB0 --- nRF24L01 MISO, pin6
+                                 +----+
+
+    ATtiny25/45/85 Pin map with CE_PIN 3 and CSN_PIN 3 => PB3 and PB4 are free to use for application
+    Circuit idea from http://nerdralph.blogspot.ca/2014/01/nrf24l01-control-with-3-attiny85-pins.html
+    Original RC combination was 1K/100nF. 22K/10nF combination worked better.
+	For best settletime delay value in RF24::csn() the timingSearch3pin.ino scatch can be used.
+    This configuration is enabled when CE_PIN and CSN_PIN are equal, e.g. both 3
+    Because CE is always high the power consumption is higher than for 5 pins solution
+                                                                                            ^^
+                                 +-\/-+           nRF24L01   CE, pin3 ------|              //
+                           PB5  1|o   |8  Vcc --- nRF24L01  VCC, pin2 ------x----------x--|<|-- 5V
+                   NC      PB3  2|    |7  PB2 --- nRF24L01  SCK, pin5 --|<|---x-[22k]--|  LED
+                   NC      PB4  3|    |6  PB1 --- nRF24L01 MOSI, pin7  1n4148 |
+    nRF24L01 GND, pin1 -x- GND  4|    |5  PB0 --- nRF24L01 MISO, pin6         |
+                        |        +----+                                       |
+                        |-----------------------------------------------||----x-- nRF24L01 CSN, pin4 
+                                                                       10nF
+
+    ATtiny24/44/84 Pin map with CE_PIN 8 and CSN_PIN 7
+	Schematic provided and successfully tested by Carmine Pastore (https://github.com/Carminepz)
                                   +-\/-+
-                   Reset/Ain0 (D 5) PB5 1|o   |8 Vcc (3v3 or -- LED -- 5v)
-    nRF24L01 CE,  Pin3 - Ain3 (D 3) PB3 2|    |7 PB2 (D 2) Ain1 - nRF24L01 SCK, pin5
-    nRF24L01 CSN, Pin4 - Ain2 (D 4) PB4 3|    |6 PB1 (D 1) pwm1 - nRF24L01 MOSI, pin7
-                                    GND 4|    |5 PB0 (D 0) pwm0 - nRF24L01 MISO, pin6
-    CE and CSN are configurable
+    nRF24L01  VCC, pin2 --- VCC  1|o   |14 GND --- nRF24L01  GND, pin1
+                            PB0  2|    |13 AREF
+                            PB1  3|    |12 PA1
+                            PB3  4|    |11 PA2 --- nRF24L01   CE, pin3
+                            PB2  5|    |10 PA3 --- nRF24L01  CSN, pin4
+                            PA7  6|    |9  PA4 --- nRF24L01  SCK, pin5
+    nRF24L01 MOSI, pin7 --- PA6  7|    |8  PA5 --- nRF24L01 MISO, pin6
+                                  +----+
 */
 
-
+// CE and CSN are configurable, specified values for ATtiny85 as connected above
 #define CE_PIN 3
 #define CSN_PIN 4
+//#define CSN_PIN 3 // uncomment for ATtiny85 3 pins solution
 
 #include "RF24.h"